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LMX2594: Undesirable Output Phase Noise

Martin Wen1
Prodigy 30 points
Part Number: LMX2594

Hello team,

I'm building up a personal project of LO using LMX2594. The register configuration is as below. The PCB schematic is referencing the LMX2594EVA including the loop filter setup. But I'm getting an undesirable phase noise around 60k across the whole output frequency band. I'm not sure which part of the design goes wrong, please help! The output RF spectrum and phase noise at 8GHz is attached below. I can provide more details if needed.

  • 0
    TI__Guru* 88320 points

    Hi Martin,

    Where is your 100MHz clock came from? Looks to me that the problem is related to the quality of the reference clock.

    BTW, in TICS Pro, when you see something turn yellow / red, mouse-over it to view the usage tips. In this case, SEG1_EN is yellow, the recommendation is to uncheck this bit.

  • 0 in reply to Noel Fung
    Prodigy 30 points

    Hi Noel,

    Thanks for the tips! I tried to put a 100uF decoupling cap to GND of the 3.3V output from LDO and problem solved. I initially had 10uF and 0.1uF to GND for the output of LDO, but it looks like it doesn't work well. I had another question about the PN performance of the LMX2594. Currently in my design, it can only achieve the phase noise of -107dBc/Hz at 100K at 8GHz output which is 6dB worse than the typical characteristic at 8GHz form data sheet. I tested with the LMX2594EVA using the same 100MHz source and signal analyzer, and I got the same result. I wonder other than getting a cleaner 100MHz source, what else could I do to improve PN. Any suggestion is appreciated, thanks!

    Best Regards,

    Martin

  • 0 in reply to Martin Wen1
    TI__Guru* 88320 points

    Hi Martin,

    The default EVM loop bandwidth is over 300kHz, so at 100kHz offset, the phase noise is going to be dominated by the PLL and reference clock. Again, you need to use a very good reference clock in order to see the real phase noise of the synthesizer.

    As for the PLL noise, use higher fpd to make N-divider smaller can reduce PLL noise. Care must be noted that there are restrictions on min. N-divider value vs MASH ORDER.

  • 0 in reply to Noel Fung
    Prodigy 30 points

    Hi Noel,

    By adjusting FPD to 200MHz does improve the phase noise at 100k for about 3dB. I'm currently trying to set the output RF to change at 1KHz step, and I found that at some fractional output the phase noise looks abnormal. Below is the phase noise I tested at 3826.501MHz, as well as the TICS configuration. By changing FPD to 100M will make the shape of phase noise look normal, but the phase noise is not good enough at 100k. 

  • 0 in reply to Martin Wen1
    TI__Guru* 88320 points

    Hi Martin,

    Your configuration will generate multiple 1kHz and 2kHz spurs from the PLL, since your loop bandwidth is more than 100kHz, you will see these spurs within the loop bandwidth. You may try to make PLL_DEN = 10000001, this may help reducing the spurs but phase noise may degrade a bit.