Hello Expert,
My customer is considering LMH1983.
We think 0x1C(Loss of Lock Threshold) and 0x2D(Lock Step Size) is the setting of judging whether PLL is locked.
In their evaluation, then they used 0x1C and 0x2D register as default setting, they sometime observed PLL is unlocked.
Would you tell me how to adjust these register's to achieve certain lock of PLL?
Their test condition is as follows.
- VDD:3.3V
- Hin:H signal input
- Vin,Fin: tied to High
- XOin: 27MHz single-ended input
I'm looking forward to hearing back from you.
Best regards,
Kazuki Kuramochi
