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LMK04828: LMK04828 - TICS Pro Software

Part Number: LMK04828
Other Parts Discussed in Thread: LMK04832, CLOCKDESIGNTOOL

Hi,

I'm trying to implement the clocking requirement in TICS Pro software.

So as per the user guide  those pins which I'm using I have to select power Down.

When I'm trying to set  clkout_8,clkout_9,clkout_10 and clkout_11 with clock 125Mhz,but its considering default value 122.8Mhz.May I know why is not setting to 125Mhz.Anything other parameter has to be enabled?

Regards,

Nireeksha

  • Hello Nireeksha,

    There is no frequency planner for LMK04828 TICS Pro profile, so you need to make updates manually.  Note the LMK04832 is very similar to LMK04828 and does have a frequency planner.  I suggest typing in the frequencies you'd like into the LMK04832 applying the frequency plan, then copy over to the LMK04828.

    Note the CLOCKDESIGNTOOL (www.ti.com/.../CLOCKDESIGNTOOL) will also calculate all the dividers needed for the LMK04828 based on requested frequencies.

    As for using the tool directly:

    While you can enter frequencies into the LMK04828, it will simply update them with the rounded, closest possible value based on current "upstream" configuration.  So with 2949.12 MHz, that means 122.88 * n type frequencies.  You need to start at the input (CLKin or OSCin) and work to the output to properly set the frequency.

    The "Set Modes" tab of the GUI will allow you to select if you want single loop or dual loop.  If you set single loop you can update the OSCin first.  If dual loop you will need to update PLL1 to have a CLKin frequency and and VCXO frequency (provided to OSCin) to support the OSCin frequency you want.

    The general idea for configuring frequency in LMK04828, is the VCO frequency of PLL2 must have an integer relationship to your output frequency.  3000 MHz / 125 MHz = 24.  I suggest 3000 MHz.

    For best performance the OSCin frequency should be a nice relationship to 3000 MHz.  For example the EVM default of 122.88 MHz VCXO doesn't have a nice relationship.  For 122.88 MHz to work with 3000 MHz a PLL2 R divider of 768 will result in a very low phase dector frequency (PDF) of 160 kHz, but then 3000 MHz VCO can be achieved.

    You'd be better off with a 100 MHz VCXO for example.  Then 100 MHz PDF will have a low integer relationship.

    73,
    Timothy