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LMK04832: Register setting

Taketo Sato
Genius 10175 points
Part Number: LMK04832

Hello team,

I have questions below about LMK04832 register setting. Could you please help to answer below?

  1. Is it ok to power down device clock digital delay function by 0x102 register(DCLKX_Y_DDLY_PD) even if we use divider path?
  2. In 0x103 register's DCLKX_Y_DCC description, it says "Required for half step" when enabling the duty cycle correction. Does this mean it will cause 0.5clk delay in case DCLKX_Y_HS=0(No phase adjust mode)? If we set DCLKX_Y_HS=1, this 0.5clk delay will be corrected and there will be no delay in the end?
  3. Regarding 0x173 register, there is different default value information on bit[4] between table 5 and table 78. Which is correct information?
  4. Default value should be written in each registers after POR. Therefore when programming a device, is it fine for user to access only necessary registers to write? or is it better to access/write all registers?
  5. Datasheet recommends to program registers in numeric order from 0x000 to 0x555, except PLL2 related register programing. However, EVM source code seems set with sequence of R386 -> R387 -> R358 -> R359 -> R360 -> R1365. Is there any meaning of the register programing sequence?

Best regards,

  • +1
    TI__Genius 12560 points

    Hi,

    Please see below the response:

    1. Yes, digital delay section is unrelated to divider and can independently disable by DCLKX_Y_DDLY_PD bit.

    2.  If DCLKX_Y_HS=1, it adjust the clock phase by half clock cycle and using the DCLKX_Y_DCC=1, it does the duty cycle correction. Hence, if want to have duty cycle correction, both bits should be high.

    3. Table 5 needs an correction with the 0x173[4] --> 1. 

    4. After setting the reset bit in the beginning, you can access / write only necessary registers. As with the POR, it sets all other registers.

    5. As mentioned in the note at section 8.5.1 in datasheet, PL2L2N registers must be programmed after other PLL2 dividers are programmed to ensure proper VCO frequency calibration. Hence, till R387, VCO frequency is calibrated and after this write PLL2_N values (R358, R359 and R360).

    Thanks!

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    TI__Genius 10175 points

    Hello Ajeet-san,

    Thank you for your comment.

    Ajeet Pal said:
    2.  If DCLKX_Y_HS=1, it adjust the clock phase by half clock cycle and using the DCLKX_Y_DCC=1, it does the duty cycle correction. Hence, if want to have duty cycle correction, both bits should be high.

    What if we set DCLKX_Y_DCC=1 and DCLKX_Y_HS=0? In this case, duty cycle is not corrected?

    Best regards,

  • 0 in reply to Ajeet Pal
    TI__Genius 10175 points

    Hello Ajeet-san,

    Thank you for your support. However, I don't understand relations of DCLKX_Y_DCC and DCLKX_Y_HS. Could you please let me know what will happen when we set DCLKX_Y_DCC=1 and DCLKX_Y_HS=0? and what will be different on duty cycle correction from condition of DCLKX_Y_DCC=1 and DCLKX_Y_HS=1?

    Best regards,

  • 0 in reply to Ajeet Pal
    TI__Genius 10175 points

    Hello Ajeet-san,

    Could you please support this additional question?

    Best regards,

  • 0 in reply to Ajeet Pal
    TI__Genius 10175 points

    Hello Ajeet-san,

    Could you let me know when you can provide a comment?

    Best regards,

  • +1 in reply to Taketo Sato
    TI__Genius 12560 points

    Hi Sato-san,

    Sorry for delayed response.

    Half clock phase adjustment needed DCLKX_Y_DCC=1 and DCLKX_Y_HS=1 and it will provide the duty cycle correction also, where DCLKX_Y_DCC=1 and DCLKX_Y_HS=0 provides the duty cycle correction but not provide the half clock cycle phase adjustment.

    Thanks!

    Regards,

    Ajeet Pal