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LMK05318B: LMK05318 two output clock config (output 180.25MHz and 24.576MHz at the same time)

Part Number: LMK05318B
Other Parts Discussed in Thread: LMK05318, , CDCE6214

Hi, I have some question for LMK05318 as below:

1. Can the 180.25Mhz used for 15" screen refer to XO output as shown below, and the 24.576Mhz used for audio refer to PRIREF output? It feels like there is no conflict between the two clock path,

2. Can it output 180.25MHz and 24.576MHz at the same time?  If so, how can it be configured?

  • Hi Wenwen,

    1. It's possible to isolate two frequencies using the non-cascaded APLL2 as long as there is a valid frequency plan available. For this mode, PLL2 has XO frequency accuracy whereas PLL1 can have reference frequency accuracy if the DPLL is enabled.
    2. The LMK05318B cannot output both 180.25 MHz and 24.576 MHz at the same time.
      1. Neither frequency cannot be sourced from VCO1 (2500 MHz) or at the same time, from VCO2 (5500-6250 MHz). 
    3. Both frequencies can be outputted using the LMK5C32216. With this device, 24.576 MHz can come from VCO3 (2457.6 MHz) and 180.25 MHz from VCO2 (5600-5950 MHz).



  • Thank you for your professional reply. The second question is 180.25MHz output from APLL2 and 24.576MHz output from APLL1, can it be done?

  • Our XO input is 24MHz, PRIREF input is 2LMK05318B_24576_18025.tcs4.576MHz, SECREF no input. But it says error, could you help to have a look? The config file is in attachment.

    " Error!
    CH7 and CH4 frequencies cannot be generated at the same time. No common multiple of the two falls within APLL1 VCO range (2.5 GHz +/- 100 ppm) or APLL2 VCO range (5.5 GHz to 6.25 GHz). "

  • Yes, the error is expected. This is what I meant that it is not possible to generate the two frequencies at the same time.

    To generate two different frequencies in the LMK05318B, these checks must pass:

    1. Determine if the desired frequencies can be generated using VCO1 (from PLL1) or VCO2 (from PLL2) frequencies.
      1. Check VCO1 (2500 MHz): 
        1. Not possible for 180.25 MHz.
          1. No integer divisor available: 2500/180.25 = 13.8696255. 
        2. Not possible for 24.576 MHz.
          1. No integer divisor available: 2500/24.576 = 101.72526.
      2. Check VCO2 (5500-6250 MHz):
        1. Possible for 180.25 MHz.
          1. VCO2 frequency options:
          2. Choose VCO2 =  5768 MHz. Integer divisor available: 5768/180.25 = 32. 
        2. Possible for 24.576 MHz.
          1. VCO2 frequency options:
          2. Choose VCO2 =  5652.48 MHz. Integer divisor available: 5768/24.576 = 230.
    2. If both desired frequencies require the same VCO, check if the two are multiples of another.
      1. Yes, they both must use VCO2 since using VCO1 cannot give the desired frequencies. However, they are not multiples of each other (as shown by TICSPRO GUI warning).
      2. This means there is no same VCO2 frequency that can be set to get both 180.25 and 24.576 MHz. Only one VCO2 frequency can be set at a given time. This is why it is not possible to configure these two frequencies at the same time on the LMK05318B.

    Is this clear?



  • Many thanks, I got it: because APLL1(VCO1) only support 2500MHz frequency, so 180.25 and 24.576 MHz will output from APLL2(VCO2) but they are not multiples of each other. 

    But why APLL1(VCO1) only support 2500MHz frequency?

  • VCO1 contains the BAW (bulk-acoustic wave) oscillator which has a fixed frequency by design (2500 MHz for the LMK05318B). VCO2 is an LC-based oscillator which allows a wider range for frequency tuning. I suggested the LMK5C32216 because it has a 2457.6 MHz BAW frequency for VCO3 and can provide the 24.576 MHz output; VCO1 or VCO2 could provide the 180.25 MHz output.


    Refer to these articles for more details on the differences between BAW and LC oscillators.



  • Thank you very much, just one more question. Why does the PLL loop can use fractional divider, but output just use integer divider? (CDCE6214 also like this)

  • That is how the part was designed. The PLL has fractional divider to work as a fraction PLL. The PLL output (VCO) gets fed into post PLL dividers which get fed into output dividers that are both integer types.