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LMX2572: VCO Lock Time Optimization

Brendon B
Prodigy 10 points
Part Number: LMX2572
Other Parts Discussed in Thread: , LMK61PD0A2

Hello,

I am currently using the LMX2572EVM to evaluate the LMX2572 for a fast frequency switching application in which we would like to hit the 5us VCO lock time for full calibration assist outlined in the LMX2572 datasheet. However, I am currently getting calibration times around 200 us in full assist mode.

The reference clock is 100 MHz generated by a LMK61PD0A2. I am running the LMX2572EVM with an SPI clock of 2 MHz (I can't go much higher with my current set up). I have double buffering enabled to minimize downtime. The procedure for a frequency change is as follows: set VCO_DACISET_FORCE and VCO_CAPCTRL_FORCE, change the PLL and channel divider as necessary for the frequency of interest, set the VCO calibration parameters and VCO_SEL_FORCE, then write to R0 to apply the new PLL parameters. I then use an oscilloscope to measure after the R0 write to when the lock pin goes high. I have LD_TYPE=1 and LD_DLY=0 to minimize LD time but still have an accurate LD reading.

I am interesting in the entire frequency band with 100 MHz output frequency steps, but I have been testing with a frequency change from 6.4 GHz to 6.4 GHz as a best case scenario.  The VCO calibration parameters are: VCO_SEL=6, VCO_DACISET=191, VCO_CAPCTRL=41.

Any suggestions on minimizing the lock time? Does the procedure seem ok? Am I measuring the lock time in a reasonable way? Is this just the performance that can be expected with the relatively slow SPI clock?

Thanks,

Brendon

  • 0
    TI__Guru* 81750 points

    Hi Brendon,

    Please do not use double buffer with full assist because we need to program R0 to execute the double-buffered registers. Since FCAL_EN=1, a VCO calibration will be triggered although the calibrated values will be overwritten by full assist.

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Hi Noel,

    Thanks that makes sense. When I remove the double buffering and R0 write, the lock time is now ~160 us. The lock bit goes high for a few us then low for the 160 us until it is stable.

    Any suggestions for how to improve this behavior with the current setup? What is the expected lock time with a 2 MHz SPI clock?

    Thanks,

    Brendon

  • 0 in reply to Brendon B
    TI__Guru* 81750 points

    Hi Brendon,

    A register write need 25 SPI clock cycles (24-bit data + 1-bit CSB). Given SPI clock cycle is 0.5µs, a register write takes 12.5µs. Assume you need to write 4 registers to change the VCO frequency, programming time will consume 50µs. 

    Programming sequence might be matter. Suggest program VCO_SEL, VCO_CAPCTRL first, then program the reset of the necessary registers. 

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Hi Noel,

    I am measuring the lock time from end of the register writes to when the lock detect goes high so the writing time is controlled for.

    Changing the order helped; the lock time is now ~ 30 us.

    Any other suggestions for reaching the 5 us lock time? Am I hitting the highest performance for the 2 MHz clock? The lock bit is down for ~30 us before the registers are done being written (my SPI protocol has some downtime between 25 bit messages).

    Thanks for your help!

    Brendon