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LMX2594EVM: Wideband Low Noise synthisizer and fast ADC

Abdulrahman Alaqeel
Prodigy 20 points
Part Number: LMX2594EVM
Other Parts Discussed in Thread: LMX2594, ADS54J64EVM, LMX2572, LMX2491, LMX2492

We are working on a prototype for an automotive sensor that works at MMW frequencies. Here are some of the questions I have in mind:

For LMX2594 EVM 15-GHz Wideband Low Noise PLL:
1- How sharp the ramp can be? Is it capable of generating 500 MHz in 10 microseconds? Let us say above 12 GHz. And in how many steps?
2- Did you perform any linearity test of such fast ramps?
3- It seems that it is a direct VCO without DDS. Can you guarantee the starting phase is matched over a sequence of many frequency ramps?
4- For fast ramps, what is the recommended settling time?
5- Is there any delay for the trigger signal? Is it fixed? What are the requirements? 
For ADS54J64EVM QuadChannel 14Bit 1GSPS and TSW14J56 JESD204B Data Capture For ADS54J64EVM:
1- What is the maximum bandwidth it can handle with 2 Channels?
2- Can you please explain the difference between:
      • Maximum Sampling Rate: 1 GSPS
      • Maximum Output Sample Rate: 500 MSPS  
3- Is there any delay for the trigger signal? Is it fixed?
4- If used without the data capture card what is the storage size?
5- Can it be triggered with LMX2594 easily, and what is your recommended controller for this purpose?
6- What is the maximum data rate TSW14J56 can handle?
7- Do you recommend any DSP hardware for basic processing to interface with max TSW14J56
These are the questions I have regarding these modules. I would appreciate detailed answers and recommendations.
  • 0
    TI__Guru* 88290 points

    Hi Abdulrahman,

    If you are looking for linear frequency ramping with 500MHz ramp range, LMX2594 or any synthesizer with built-in VCO is not a good choice. You need to use discrete PLL, such as LMX2491 or LMX2492, + external VCO. LMX2594 can support approx. 100MHz linear frequency ramp range. A higher ramp range will requires a VCO calibration, as a result, the ramp is not linear but a staircase ramp. For details, please read LMX2572 datasheet.

    Please post ADC questions to the Data Converters forum.

  • 0 in reply to Noel Fung
    Prodigy 20 points

    Thank you Noel for directing me toward the right board.

    If I go with the LMX2492.

     - Can it chirp over the 500MHz in 10 micro-sec?

    - Did you perform any linearity test of such fast ramps?
    - It seems that it is a direct VCO without DDS. Can you guarantee the starting phase is matched over a sequence of many frequency ramps?
    - For fast ramps, what is the recommended settling time?
    - Is there any delay for the trigger signal? Is it fixed? What are the requirements? 

    I appreciate your helping with these questions.

  • 0 in reply to Abdulrahman Alaqeel
    TI__Guru* 88290 points

    Hi Abdulrahman,

    From the device configuration point of view, it is possible to ramp 500MHz in 10µs. 

    In practice, the loop bandwidth should be wide enough or otherwise we may not get linear ramp.

    LMX2492 is typical analog PLL. During ramping, the internal ramp engine will increase PLL_NUM and PLL_N to change (external) VCO frequency. If the VCO frequency is an integer multiple of the PLL reference clock, I think the phase between VCO and reference clock is deterministic. We never did phase measurement, we don't have any test data.

    What trigger did you mean?

  • 0 in reply to Noel Fung
    Prodigy 20 points

    For the phase: if i want to generate a train of ramps (like a sawtooth signal) how can I insure that the starting phase of the starting frequency of each ramp is matched for all ramps? does it start the PLL reference clock for each ramp and at a fixed phase?

    By trigger, I mean arming or starting the ramping. The time from point of sending the signal to start ramping until the ramp is at RF output, is this time deterministic?

  • 0 in reply to Abdulrahman Alaqeel
    TI__Guru* 88290 points

    Hi Abdulrahman,

    I don't know the phase issue, our ramp engine changes the N divider value during ramp, we have never do any phase alignment. The ramp time is deterministic as the ramp is running at the phase detect frequency. For example, if fpd = 100MHz, the ramp engine will increment N divider once every 10ns.