LMK1D1208P: Problems with 1204 and 1208P clock chips

...

Hi,

Could you provide me some more information about your two question? so I can better assist. 

?? ? said:

Problem 1: LMK1D1208P is used as the clock buffer. Three 100Ms from the same chip are used as the system clock of three FPGAs. Two of them are OK. One of them has a problem with the clock when debugging DDR3. After replacing the system clock, there will be no problem. The DC coupling method is used:

By system clock, do you mean clock source was changed and it started working fine?

?? ? said:

Problem 2: Two LMK1D1204 chips, 156.25M and 100M, are used to provide clocks for the high-speed ports BANK116 and BANK115 of the FPGA. The 156.25M BANK116 clock is not locked, and the 100M BANK115 is used to lock. When the 100M BANK116 is used, it is also locked,:

For 156.25MHz, what are the locking requirement for FPGA or input requirements , do you see a good clock from LMK1D1204 when probing the outputs?

I do see that for LMK1D1204 100MHz case. Input termination might not be good with AC coupling because your common mode voltage is 0V. Minimum input common mode voltage requirement for input is 0.25V.

Best,

Asim

Problem 1 is that the clock source has changed,

There is no problem with 100M AC coupling in question 2. On the contrary, there is a problem with 156.25 DC coupling. Attempts have also been made to change DC coupling to AC coupling, which has no effect

Problem 1 is that the clock source has changed,

There is no problem with 100M AC coupling in question 2. On the contrary, there is a problem with 156.25 DC coupling. Attempts have also been made to change DC coupling to AC coupling, which has no effect

Hi Asim, thanks for your patience, I have another question, if these problems related with wire lengths? the length of these abnormal signals wire (4000+ mil) is 1.5~2 times to the normal ones (2000+ mil), will it affect the work?

Hi Shengyue,

I don't think the trace length should have any affect on it. Could you probe the inputs and outputs of buffer if possible to provide a screenshot? 156.25MHz should work fine. Btw AC coupling method might be out of spec for VCM which could degrade performance.

Best,

Asim

Hi Asim, both of them are DC coupling.

LMK1D1208P: one piece, use three outputs at the same frequency 100MHz, all connected to different FPGAs (with DDR), two of them are work perfectly, the last one is not work out, when the "abnormal" FPGA use the two normal buffered clocks, it also works well, the problem output (out2) wave is not as good as the normal ones (out1, out3), wave amplitude are similar with each other.

LMK1D1204: two pcs, one is used for 100MHz (good one), one is used for 156.25MHz (the problem one), please check test result below, ignore the overlaps which caused by improper time scope.

Amplitude of 100MHz changed after through the buffer, but amplitude of 156.25MHz was not changed a lot and wave shape worsened.

Hi Shengyue,

LMK1D1208P:

In the schematic you shared, i don't see a 100 Ohm termination. Do your FPGA's have that integrated? Note, that you should place the 100 Ohm close to the receiver and not close to the buffer.

LMK1D1204:

the oscilloscope pictures show very low signal amplitude. Did you measure the output close to the receiver chip? Did you use a 1:10 probe?

Also to avoid these double images you should place the trigger inside the waveform.

From your schematic i can see that the 100MHz OSC is not terminated. This causes reflections and results in higher swing.

In general your input signal looks like a triangular waveform for both 100MHz and 156.25MHz which does not seem correct.

For the 156.25MHz, do you need to change the parameters inside the FPGA that it will lock with that frequency?

Regards,

Julian

A side note: TI is going to release BAW based Oscillators, which you can use as drop in for your current XO's. See more information here: https://www.ti.com/product/LMK6C

Hi Julian,

Julian Hagedorn said:

that you should place the 100 Ohm close to the receiver and not close to the buffer

1. If 100 Ohm resistor is close to the buffer but not receiver, will it possible affect the quality of signals and lead to FPGA startup fails finally?

Julian Hagedorn said:

From your schematic i can see that the 100MHz OSC is not terminated. This causes reflections and results in higher swing.

In general your input signal looks like a triangular waveform for both 100MHz and 156.25MHz which does not seem correct.

For the 156.25MHz, do you need to change the parameters inside the FPGA that it will lock with that frequency?

2. The weird thing is although 100MHz is not properly designed, it still works well.  As you mentioned triangular waveform, is that means maybe it's the OSC output problems?

3. Actually, the FPGA is on boot (not so sure) mode, it should lock at any frequency without any different settings, please check FPGA datasheet below. ds182_Kintex_7_Data_Sheet.pdf • Viewer • Documentation Portal (xilinx.com)

As the information and schematic are from my customer, so there will be a little bit delay for communication, thanks for your patience.

Hi Shengyue,

not ideally terminated clock signals may have reflections and can cause noise that the receiver cannot interpret the LOW/HIGH levels correct.

Also with these long traces the clock may pick up noise which then exceeds the FPGA phase noise requirements.

LMK1D1208P:

is that faulty clock signal routed close to DCDC power supplies or other noisy circuits?

Please also check if the signal levels at the FPGA input pins are in the datasheet specs (FPGA).

I am not an FPGA expert, but i guess that you need to change PLL settings when you change the input frequency into the device.

regards,

Julian

Hi Julia,

Thanks for your answer, one more question: Is there any device or layout tip could help to eliminate possible reflections and noise in future clock circuit design, when termination is not ideally?