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LMK00308: Min/Max Jitter at HCSL

Kazuhiko Hirano
Genius 11643 points
Part Number: LMK00308

Hello

Q1:
My customer would like to know the maximum value of JitterADD for HCSL OUTPUT at Vcco=3.3V, RT=50ohms to GND, CLKin=100MHz and Slew rate >= 3Vns. (the datasheet specifies typical value is 77fs)

Q2:
How much is the minimum and the maximum cycle to cycle jitter for HCSL OUTPUT at Vcco=3.3V, RT=50ohms to GND, CLKin=100MHz and Slew rate >= 3Vns?

Best regards,

K.Hirano

  • 0
    TI__Expert 7735 points

    Hello Kazuhiko,

    1) If no minimum or maximum value are listed in the data sheet, that means there is no minimum or maximum values that will damage the part or performance for that characteristic.

    2) I am currently trying to get the data for this.

    Best,

    Andrea

  • +1
    TI__Genius 9250 points

    Hi Kazuhiko,

    We currently don't have minimum and maximum data over PVT since this is an old part and data was collected for typical silicon as defined in datasheet. I can check with the team to see if we can find PVT simulation data that could help estimate these values. 

    Cycle to cycle is usually not specified for buffer devices. They just add some phase jitter so we usually have additive phase jitter specification in the datasheet.

    Best,

    Asim