LMK04828BEVM: Inquiry while using Clk0 port pulse mode.

Hong Sung Dae

Part Number: LMK04828BEVM

I configured it with evkit as shown in the picture below.

After setting pulse mode using clk0 port, SDclkout outputs undesirable signal in signal standby state.

If the LVDS signal of the FPGA EVKIT is separated, it is output stably to SDCLKOUT.

clk0 : bipolar mode
SDCLKOUT : LVDS OUT

Also, when continuous signal is applied, it operates normally.

Also, by changing CLK0 to MOS mode, it is normal when waiting for signals.

What will be the solution at this time?

0 Julian Hagedorn over 3 years ago

Hello,

In order to use pulser mode, you would need to replace the AC coupling on the EVM input to a DC coupling.

Regards,

Julian

0 Hong Sung Dae over 3 years ago in reply to Julian Hagedorn

Hello,

Thank you for answer.

I am curious about the application of DC coupling.
For example, the wiring method of LVDS, CML, and LVPECL signals.

Regards,

Sungdae.

0 Ajeet Pal over 3 years ago in reply to Hong Sung Dae

Hi,

For the DC coupled input at CLKin0, can provide the LVDS format input.

Thanks!

Regards,
Ajeet Pal

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