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LMK04828BEVM: Inquiry while using Clk0 port pulse mode.

Part Number: LMK04828BEVM

I configured it with evkit as shown in the picture below.

After setting pulse mode using clk0 port, SDclkout outputs undesirable signal in signal standby state.

If the LVDS signal of the FPGA EVKIT is separated, it is output stably to SDCLKOUT.

clk0 : bipolar mode
SDCLKOUT : LVDS OUT

Also, when continuous signal is applied, it operates normally.

Also, by changing CLK0 to MOS mode, it is normal when waiting for signals.

What will be the solution at this time?