Hi, Support Team
We have question about for CDCDB2000NPPR
Could we fine tune rising /falling time slowly by register?
Fail item:
TI CDCDB2000
3. CPU1_BCLK0 (SKU3): Diff rising/falling slew rates are out of spec.
7. 1U_Riser (SKU3): Diff rising/falling slew rates are out of spec.
8. 2U_Riser_Port0 (SKU3): Diff rising/falling slew rates are out of spec.
9. 2U_Riser_Port1 (SKU3): Diff rising/falling slew rates are out of spec.
10. M2 Riser_J1 (SKU3): Diff rising/falling slew rates are out of spec.
11. M2 Riser_J2 (SKU3): Diff rising/falling slew rates are out of spec.
12. LOM_100M (SKU3): Diff rising/falling slew rates are out of spec.
For example fail below
According to the Eagle Stream Platform EDS Rev 2.0, the maximum of slew rate is 4 V/ns.
so about the slew rate is can not meet the Intel EDS?
if any suggestion, Please advise me.
Thanks,
Best regards,
Lawrence