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I am looking for a recommendation for a chip to clean up jitter on an LVDS serial MCLK signal from an FPGA. The MCLK frequency is typically between 40 and 80 MHz. The output needs to be DC-coupled LVDS with RMS jitter less than 1ps. I also really only need a single output per input (up to 2 potential clocks in, 2 potential clocks out).
I have seen recommendations for LMK04906 but it is potentially more complicated than we need.
-Ben
Hi Ben,
You can look into LMK5B12204 device which had lower output count for your requirements. For jitter cleaner, we usually have higher output count devices.
Best,
Asim
Thank you for this recommendation. Pardon my ignorance, but this chip has AC-coupled LVDS outputs and we typically require DC-coupled LVDS, what is required to use this with DC-coupled LVDS?
Hi Ben,
You are right on that. I missed that detail while recommending that part. I am forwarding this request to subject matter expert who would better assist with all your inquiries and details.
Best,
Asim
Hi Ben,
There are multiple LVDS interface jitter cleaner parts and you can use the Clock Tree Architecture Tool to find the available solution.
You can have a look on the LMK04228, LMK04828 and LMK04832, those all are supporting 80MHz LVDS output with the jitter better than 100/200fs.
Thanks!
Regards,
Ajeet Pal