I am looking for a recommendation for a chip to clean up jitter on an LVDS serial MCLK signal from an FPGA. The MCLK frequency is typically between 40 and 80 MHz. The output needs to be DC-coupled LVDS with RMS jitter less than 1ps. I also really only need a single output per input (up to 2 potential clocks in, 2 potential clocks out).
I have seen recommendations for LMK04906 but it is potentially more complicated than we need.
-Ben