LMK05318BEVM: How to achieve phase synchronization of the input and output clocks

Amy,

I will let Riley respond.

Regards,
Jennifer

Hi Amy,

There is option to use either XO + APLL2 only or use DPLL with APLL2 in cascaded mode to minimize APLL2 in-band phase noise/jitter impact from XO. Could you share jitter requirement for the output clock?

Also, another advantage of using DPLL is that it allows hitless switchover when one of the references is lost. Let us know which option you would like to have for the config.

-Riley

Hi Riley,

Glad to see your reply.  Here's what I've received from the customer. Could you please give your comments 

Riley Nguyen said:

There is option to use either XO + APLL2 only or use DPLL with APLL2 in cascaded mode to minimize APLL2 in-band phase noise/jitter impact from XO. Could you share jitter requirement for the output clock?

There is no requirement for output clock jitter. Just keep up with the phase change of the input clock as soon as possible. Which parameter setting is related to the phase synchronization speed? In addition, how to set XO+APLL2 or cascade mode?

Riley Nguyen said:

Also, another advantage of using DPLL is that it allows hitless switchover when one of the references is lost. Let us know which option you would like to have for the config

We only have one input reference clock, which cannot be switched. Therefore, whether the input clock meets the requirements or not, the output clock phase must follow the input clock change.

Best Regards,

Amy

Hi Amy,

You don't need to use DPLL in this case. The 49.152-MHz output of APLL2 can be phase-locked to the XO input 12.288 MHz. I would recommend to use APLL-only parts such as: LMK03318 or CDCE6214 (has ZDM feature). If you need the output to have deterministic phase lock to the input, then ZDM is needed.

You can set XO = 12.288 MHz and use APLL2 to generate the 49.152-MHz output.

Let me know which part you would like to use so I can help with the config.

-Riley

Hi Riley,

Thank you for your support. 

The following is the customer feedback:

We cannot use XO for clock input. The 12.288M clock we input is the clock signal extracted by the line. The phase sometimes produces a quarter of a cycle shift, which is related to the line data and cannot be replaced by XO. It is required that the 49.152M clock phase output be synchronized with the input clock as soon as possible in the following dozens of cycles. Can LMK05318B be implemented and how to set it?

Please let me know your thought on this.

Best Regards,

Amy

Hi Amy,

The LMK05318B EVM has an on-board XO and will not be used. Instead, we would use the 12.288-MHz as an external XO input through pin XO_P (single-ended) or XO_P/N (differential). The on-board XO needs to be powered down by shorting pin 2-3 of jumper J9 (picture attached).

On TICS Pro LMK05318B:

- Set XO frequency (Hz) = 12.288e6. Choose interface type according to the input buffer.

I would recommend to ensure the 12.288 MHz input clock meets the XO input characteristics:

- Set target frequency of 49.152 MHz and the output format. You can also disable other inputs, then calculate frequency plan. APLL2 will be selected to generate this output clock from the 12.288 MHz input.

- Disable PRIREF and SECREF as DPLL is not in use.

- You can run the config with "Ctrl + L" and "Soft-reset Chip" and check the output frequency.

Let me know if you need help. We can provide .tcs config file if needed.

-Riley

Whether the DPLL or APLL1 needs to be enabled,except for what you said above? I hope you can provide .tcs config file.

7457.LMK05318B TICS Pro GUI Overview.pdf
Hi Lixiaoling,

Could you clarify what you mean by this?

lixiaoling0110 said:

Whether the DPLL or APLL1 needs to be enabled,except for what you said above?

Attachment is the instruction to use LMK05318B TICS Pro. You can try to make the config with steps in my previous reply.

-Riley

Hi Riley,

Thank you for your support over this time. However, our this customer encounter the following problems, could you please continue to provide assistance

After I follow the settings in your screenshot above, other parameters are configured by default, and the output clock and input clock phases cannot be synchronized. Is it because the default configuration of the reference clock of APLL2 in the wizard configuration page is VCO1? If the reference clock of APLL2 is changed to XO, the output clock has no signal. Apart from the parameters in your screenshot, do I need to change other parameters? I need you to provide a. tcs configuration file.

Thanks,

Amy

Hi Amy,

I'll get back with the config next week.

-Riley

Hi Riley,

Sorry for pushing you, any update on here?

Hi Amy,

Please try this config: XO_12.288MHz_Out_49.152MHz.tcs

-Riley