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LMK04832-SP: LMK04832W/EM PLL Lock

Gerald
Genius 9575 points
Part Number: LMK04832-SP

Hi Experts,

If the customer is using the LMK to receive a clock on fin0/fin0* will the clock only be used with PLL2? Also, if he would like to detect if PLL2 is locked would Status_LD2 only indicate PLL2 status or can it indicate if PLL1 and PLL2 are locked? Would this signal be logic high if the PLL is locked?

Please advise. Thank you.

Best regards,
Gerald

  • +1
    TI__Genius 9750 points

    Hi Gerald,

    I'm new to this part but I'll do my best to support this since our resident jitter cleaner specialist is out on rotation. As I understand, if a generic clock input is received by Fin0/Fin0*, it just gets forwarded to the VCO Mux as a selectable source for the clock distribution stage, so its operation is typically not related to either of the PLLs. The datasheet details an application example (8.4.2.2) where PLL2 is being used in a single-loop mode with an external loop filter and external VCO; in this specific case, Fin0/Fin0* can be used to receive the signal from the external VCO and feed it back into PLL2 and the distribution network. PLL1 should be unused and Fin0/Fin* has no effect on it. But it doesn't quite sound like your customer is doing that based on what you said.

    Status_LD2 can be configured to indicate both whether PLL2 is locked or not, and also whether both PLL1 and PLL2 are locked, through the Digital Lock Detect (DLD) functionality. Section (8.6.2.8.7) of the datasheet shows the programming options available for this pin, I think the two relevant options are "PLL2 DLD" and "PLL1 & PLL2 DLD". I expect this signal to be logic high if the PLL is locked and logic low if not.

    Thanks,

    Evan Su