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LMK00804B: Single-Ended/LVCMOS Input DC Bias

Part Number: LMK00804B

Hi team,

In TI's 4xAWR2243 cascaded imaging radar reference design TIDEP-01012 reference design | TI.com, the LMK00804B's nCLK input is DC-biased to 0.7V with resistor ladders as below: 

the 40M_BUF_ IN_ PRIMAWRY clock is from AWR_1_OSC_CLKOUT, which is a gound to 1.4V swinging square wave.

And I was little confued about the input DC-bias,  WHY the Non-inverting differential clock input is not DC biased to 0.7V? Isn't  it supposed to both differential clock inputs are DC-biased?

  • Hi Andy,

    Non-inverting input biased in the datasheet is done to reduce the input swing of 3.3 V to stay in the single ended swing requirements of the buffer. In this example we don't need that because swing is well below the datasheet requirements (based on VID specs). One other thing to notice is that they have a slight offset between inputs which keeps outputs low when there is no clock.

    Best,

    Asim