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CDCV304: Ringing in CDCV304 buffer output

Mohan Kumar P
Prodigy 20 points
Part Number: CDCV304

Hi

              We are using two CDCV304 clock buffer in same control card and we are getting different waveforms from these 2 buffer outputs.

These 2 buffer output is going to same receiver with 33 ohms termination. For 1 buffer clock output there were no ringing & as for other output ringing is there. Attached the waveform below.

 

S.No

Net name

CLK Freq

Driver

Receiver

Series R

TL length from Driver to Rx

Captured Waveform

1

CLK_10M_20M_1588_OCXO

20M

CDCV1

Xilinx Kintex 7 FPGA

33 ohms

16.2 inch

2

CLK_125M_APLL_1588_FBCK

125M

CDCV2

Xilinx Kintex 7 FPGA

33 ohms

3.8 inch

3

20MHZ_PLL_OSC_CLK

20M

CDCV1

RC 8A35036 SMU

33 ohms

9.6 inch

4

CLK_125M_PLL_1588_FBCK

125M

CDCV2

RC 8A35036 SMU

33 ohms

4 inch

 

 

By varying the termination resistor value to 22 ohm, 18 ohm, 10 ohm still we are seeing ringing with overshoot & undershoot in the waveform.

 

I have checked the input clock for CDCV304 (CDCV1) and it is fine, attached the same here for your reference.

 

Load circuit test given in the datasheet is for 70 ohms instead of standard transmission line impedance of 50 ohms.

Our PCB traces are routed using 50 ohm impedance. Do you think this could have caused the issue?

 

Kindly help us understand the reason for the ringing.

 

Thanks

Mohan

  • 0
    TI__Genius 9250 points

    Hi Mohan,

    Could you please share your schematic and layout as well? I am going to run few sims to understand this behavior. For LVCMOS we can match the impedance to get better signal without undershoot and overshoot. This buffer has an output impedance of around 25 ohms so Rs = 25 ohm on the output can be good resistor value for matching the transmission lines. I can run sims using IBIS to get optimum resistor to well match the network.

    What type of probe you are using for these measurements. How long is the gnd pin loop? This could further narrow it down if its a measurement issue.

    Ringing could be due to power supply as well. We can make make sure that the filtering network is good and there is no ripple being coupled at the VDD pins. 

    Best,

    Asim 

  • 0 in reply to Asim Khan
    Prodigy 20 points

    Hi Asim

          I have attached the screenshots for the same below,

    S.No Driver Net name Rs Length Driver Schematic Driver Layout
    1 CDCV1(U186) CLK_10M_20M_1588_OCXO 85mils    
    20MHZ_PLL_OSC_CLK 95.4mils
    2 CDCV2(U184) CLK_125M_APLL_1588_FBCK 62.4mils    
    CLK_125M_PLL_1588_FBCK 85mils

    Receiver

    RC 8A35036 SMU- Schematic                                                                                              RC 8A35036 SMU - Layout

    Xilinx Kintex 7 FPGA - Schematic                                                                                               Xilinx Kintex 7 FPGA - Layout

                                              

     

     1. Query on Probing/measurement: We are using E2677 soldering tips and N1169B probe adapter, so there is no question of longer GND loop. Besides, same measurement setup gives a clean clock for CDCV output in 1 case and gives a CLK with ringing for CDCV output in another case.

    2. Query on Power Supply: While you check on the simulation and get a suitable value, we will try to check this and get back to you. But from the SCHM, we have added a ferrite and sufficient decaps, so we don't expect an issue there. 

    Thanks

    Mohan

  • 0 in reply to Mohan Kumar P
    TI__Genius 14715 points

    Hi Mohan,

    Thanks for the information, Asim is out of the office now but we will try to get back to you tomorrow.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    TI__Genius 9250 points

    Hi Mohan,

    I ran some IBIS sims based on your trace length. Series resistor of 33 ohm should be fine for this. Can we get some more information on the layout side. I want to check how how far are decoupling caps from the power pin? 

    Best,

    Asim

  • 0 in reply to Asim Khan
    Prodigy 20 points

    Hi Asim

          I have attached the screenshots of decaps for both the buffers below & caps are placed close to the buffer.

    CDCV1 - U186

    CDCV2 - U184


    Thanks

    Mohan

  • 0 in reply to Mohan Kumar P
    TI__Genius 9250 points

    Hi Mohan,

    They look fairly close to the DUT. I have ordered EVM which should arrive by early next week to do lab experiments. I will provide an update on it soon.

    Best,

    Asim

  • 0 in reply to Asim Khan
    TI__Genius 9250 points

    Hi Mohan,

    I am sorry for delayed response on this thread. I have done some experiments and found out that we could get rid of the ringing that's happening on this buffer. 

    I think this ringing which is really high frequency of about 300 MHz as I measured on my EVM in the lab is coming from inductance on the VDD pins of this buffer. Due to long bond wires on the VDD pin we probably have more inductance on that pin. Since all outputs switch at the same time, this affect of L due to switching current shows more prominent.

    Although this peaking is not causing any issue in the system since its smaller to cause any issue for threshold level. It can be eliminated using higher series resistors and capacitive loading on all the outputs. 

    Few of things that I tried during the debug and found a useful scenario where I was able to get rid of it.

    1. I did multiple experiments with decoupling caps based on the ringing frequency but it that didn't help.
    2. Tried series resistor from 25 to 33 as you used in your setup with out any capacitive loading. I saw similar results like you.
    3. Tried capacitive loading recommended for this device with 33 and 25 ohm. It helped but there was still some ripple.
    4. Tried 50 ohm series resistor with 10 pF loading on all outputs to reduce the current and help spread current transients. This gave the best results and help remove ringing on the waveform. I would suggest trying this on your board and see if it helps.

    Below are some of the results:

    Rs  = 50 ohm   CL = 10 pF cap ---> Ringing almost gone. 

    Rs  = 50 ohm   CL = 0 pF cap ---> Ringing noticed

    Rs  = 25 ohm   CL = 10 pF cap ---> Ringing noticed


    Best,

    Asim