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LMK04828: Lmk04828 Output Clock stability check

Soumya Mishra
Prodigy 50 points
Part Number: LMK04828
Other Parts Discussed in Thread: ADC32RF45,

We are trying jesd interface between adc32rf45 and stratix 10 intel fpga, but we are not able to acheive link between adc and fpga.

So, we tried jesd ip core with loopback condition, but we are not able to get the ATX PLL(ip core) lock output using the transciever clock(one of the output clock from lmk04828) as input reference clock. 

As lock is not happening,we are not sure that  transciever clock is stable. 

So, we have done some tests to check the clock stablity.

Below we have attached our LMK configuration and test results for checking stability.

Can someone please tell us that what could be the issue for not locking.

LMK_SETTINGS.docx

  • 0
    TI__Mastermind 18950 points

    Hi Soumya,

    We have paged a device expert.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    TI__Genius 12560 points

    Hi Soumya,

    OSCin should be AC coupled with 50ohm termination for single ended input, it does have internal common mode level. In your setup, it is connected with higher common mode voltage (CMOS) from OSCout.

    This could cause of signal integrity issue and deviating the output frequency.

     

    I could suggest to take the OSCout output (LVPECL format) after C2211 and connect to OSCINP, C2212 with 50ohm to GND after disconnecting the FPGA_OSCOUT signal. Keep the C2206 as OSCINN pin.

    Thanks!

    Regards,

    Ajeet Pal

    Edited: LMK04828 CMOS can support < 250MHz output frequency.

  • 0 in reply to Ajeet Pal
    Prodigy 50 points

    Hi Ajeet,

    Thank you for your valuable input.

    As per your suggestion we have done some changes. PFA

    LMK_CLOCK_TEST.docx

    Regards

    Soumya

  • 0 in reply to Soumya Mishra
    TI__Genius 12560 points

    Hi Soumya,

    I apologies for the correction on above response. The CMOS output can be maximum of 250MHz, instead of minimum. so the frequency selection was fine. But OSCin can't have OSCout LVCMOS output as input. LVCMOS has higher swing than OSCin expected.

    Also, PLL2 has the maximum phase detector frequency up to 155MHz. So with the 300MHz reference frequency, you can use the PLL2_R value "2" to reduce the phase detector frequency 150MHz.

    With the given pull down settings for LVPECL, you can use the same frequency for OSCout LVPECL output format.

    As I suggested earlier, you can have R1433 and R1422 as it is 240ohm and can keep 50ohm resistor at C2207.

    Thanks!

    Regards,

    Ajeet Pal