Hi
Good Evening
I am facing a strange problem with this LVDS buffer. In my design , I have used 2 such buffer. The design includes 40 MHz generation from quad channel DDS . 2 channels at 40 MHz us fed to two separate LMK buffers. The input power level is -7dBm and frequency is 40 MHz. I have evaluated the chip standalone with differential CRO probes in Lecroy CRO and the design works fine .
Now the LVDS output from these two buffers goes to system through backplane and cable assembly. What I observe is , in system the output of LVDS goes almost near the noise floor for around 200 ns and this behaviour is observed at random . Behaviour is common for both LMKs .
As the LMK has other pins , I have enabled and checked , other pins which doesn’t go to system works fine.
Any clue ?
Regards
Vikas
