Other Parts Discussed in Thread: LMK05318B
I have tryed to following clock generation on the EVB.
Settings and puopose
- Input 12.8 MHz from 50ppm SG to XO
Input 10 Hz from 50ppm SG to PRIREF
Output 8 MHz synchronized to PRIREF edge to OUT7P
The settings are as follows: XO12.8M_REF10 Hz_OUT7_8M.tcs
Result - Holdover and does not accept PRIREF
* I understand that additional settings are required to synchronize the 8 MHz output to the edge of PRIREF, but I will consider synchronizing the current frequency and plan to add additional settings after that.
XO12.8M_REF10 Hz_OUT7_8M.tcs
[SETUP]
ADDRESS=888
CLOCK=8
DATA=4
LE=2
PART=LMK05318B
IFACE=I2C
ADDRESS_I2C=0x65
INTERFACE_SPEED=400
[PINS]
PINNAME00=REFSEL
LOCATION00=9
PINVALUE00=False
PINNAME01=HW_CTRL
LOCATION01=7
PINVALUE01=False
PINNAME02=PDN
LOCATION02=3
PINVALUE02=True
PINNAME03=GPIO0
LOCATION03=8
PINVALUE03=False
PINNAME04=GPIO1
LOCATION04=6
PINVALUE04=False
PINNAME05=GPIO2
LOCATION05=5
PINVALUE05=False
PINNAME06=Status0
LOCATION06=10
PINVALUE06=False
PINNAME07=Status1
LOCATION07=11
PINVALUE07=False
[MODES]
NAME00=R0
VALUE00=16
NAME01=R1
VALUE01=267
NAME02=R2
VALUE02=565
NAME03=R3
VALUE03=834
NAME04=R4
VALUE04=1038
NAME05=R5
VALUE05=1284
NAME06=R6
VALUE06=1560
NAME07=R7
VALUE07=1934
NAME08=R8
VALUE08=2050
NAME09=R10
VALUE09=2760
NAME10=R11
VALUE10=2816
NAME11=R12
VALUE11=3099
NAME12=R13
VALUE12=3328
NAME13=R14
VALUE13=3776
NAME14=R15
VALUE14=3840
NAME15=R16
VALUE15=4096
NAME16=R17
VALUE16=4381
NAME17=R18
VALUE17=4863
NAME18=R19
VALUE18=4877
NAME19=R20
VALUE19=5336
NAME20=R21
VALUE20=5377
NAME21=R22
VALUE21=5632
NAME22=R23
VALUE22=5973
NAME23=R24
VALUE23=6229
NAME24=R25
VALUE24=6400
NAME25=R26
VALUE25=6656
NAME26=R27
VALUE26=6912
NAME27=R28
VALUE27=7169
NAME28=R29
VALUE28=7443
NAME29=R30
VALUE29=7744
NAME30=R32
VALUE30=8260
NAME31=R35
VALUE31=8960
NAME32=R36
VALUE32=9219
NAME33=R37
VALUE33=9472
NAME34=R38
VALUE34=9728
NAME35=R39
VALUE35=9986
NAME36=R40
VALUE36=10255
NAME37=R41
VALUE37=10496
NAME38=R42
VALUE38=10769
NAME39=R43
VALUE39=11202
NAME40=R44
VALUE40=11264
NAME41=R45
VALUE41=11524
NAME42=R46
VALUE42=11793
NAME43=R47
VALUE43=12039
NAME44=R48
VALUE44=12362
NAME45=R49
VALUE45=12585
NAME46=R50
VALUE46=12831
NAME47=R51
VALUE47=13056
NAME48=R52
VALUE48=13312
NAME49=R53
VALUE49=13583
NAME50=R54
VALUE50=13824
NAME51=R55
VALUE51=14080
NAME52=R56
VALUE52=14351
NAME53=R57
VALUE53=14592
NAME54=R58
VALUE54=14863
NAME55=R59
VALUE55=15104
NAME56=R60
VALUE56=15375
NAME57=R61
VALUE57=15616
NAME58=R62
VALUE58=15887
NAME59=R63
VALUE59=16318
NAME60=R64
VALUE60=16384
NAME61=R65
VALUE61=16640
NAME62=R66
VALUE62=16896
NAME63=R67
VALUE63=17397
NAME64=R68
VALUE64=17416
NAME65=R69
VALUE65=17664
NAME66=R70
VALUE66=17920
NAME67=R71
VALUE67=18176
NAME68=R72
VALUE68=18483
NAME69=R73
VALUE69=18688
NAME70=R74
VALUE70=18944
NAME71=R75
VALUE71=19200
NAME72=R76
VALUE72=19456
NAME73=R77
VALUE73=19727
NAME74=R78
VALUE74=19968
NAME75=R79
VALUE75=20225
NAME76=R80
VALUE76=20480
NAME77=R81
VALUE77=20746
NAME78=R82
VALUE78=20992
NAME79=R83
VALUE79=21255
NAME80=R84
VALUE80=21632
NAME81=R85
VALUE81=21760
NAME82=R86
VALUE82=22016
NAME83=R87
VALUE83=22302
NAME84=R88
VALUE84=22660
NAME85=R89
VALUE85=22912
NAME86=R90
VALUE86=23040
NAME87=R91
VALUE87=23316
NAME88=R92
VALUE88=23552
NAME89=R93
VALUE89=23815
NAME90=R94
VALUE90=24192
NAME91=R95
VALUE91=24320
NAME92=R96
VALUE92=24576
NAME93=R97
VALUE93=24862
NAME94=R98
VALUE94=25220
NAME95=R99
VALUE95=25472
NAME96=R100
VALUE96=25640
NAME97=R101
VALUE97=25857
NAME98=R102
VALUE98=26146
NAME99=R103
VALUE99=26383
NAME100=R104
VALUE100=26655
NAME101=R105
VALUE101=26885
NAME102=R106
VALUE102=27136
NAME103=R107
VALUE103=27492
NAME104=R108
VALUE104=27648
NAME105=R109
VALUE105=28001
NAME106=R110
VALUE106=28328
NAME107=R111
VALUE107=28416
NAME108=R112
VALUE108=28672
NAME109=R113
VALUE109=28928
NAME110=R114
VALUE110=29184
NAME111=R115
VALUE111=29443
NAME112=R116
VALUE112=29697
NAME113=R117
VALUE113=29952
NAME114=R118
VALUE114=30208
NAME115=R119
VALUE115=30464
NAME116=R120
VALUE116=30720
NAME117=R121
VALUE117=30976
NAME118=R122
VALUE118=31232
NAME119=R123
VALUE119=31528
NAME120=R124
VALUE120=31744
NAME121=R125
VALUE121=32017
NAME122=R126
VALUE122=32377
NAME123=R127
VALUE123=32634
NAME124=R128
VALUE124=32768
NAME125=R129
VALUE125=33025
NAME126=R130
VALUE126=33280
NAME127=R131
VALUE127=33537
NAME128=R132
VALUE128=33793
NAME129=R133
VALUE129=34167
NAME130=R134
VALUE130=34304
NAME131=R135
VALUE131=34602
NAME132=R136
VALUE132=34816
NAME133=R137
VALUE133=35196
NAME134=R138
VALUE134=35384
NAME135=R139
VALUE135=35587
NAME136=R140
VALUE136=35842
NAME137=R141
VALUE137=36096
NAME138=R142
VALUE138=36353
NAME139=R143
VALUE139=36609
NAME140=R144
VALUE140=36983
NAME141=R145
VALUE141=37121
NAME142=R146
VALUE142=37513
NAME143=R147
VALUE143=37664
NAME144=R149
VALUE144=38157
NAME145=R150
VALUE145=38400
NAME146=R151
VALUE146=38657
NAME147=R152
VALUE147=38925
NAME148=R153
VALUE148=39209
NAME149=R154
VALUE149=39460
NAME150=R155
VALUE150=39730
NAME151=R156
VALUE151=39937
NAME152=R157
VALUE152=40192
NAME153=R158
VALUE153=40448
NAME154=R159
VALUE154=40704
NAME155=R160
VALUE155=41212
NAME156=R161
VALUE156=41266
NAME157=R162
VALUE157=41472
NAME158=R164
VALUE158=41984
NAME159=R165
VALUE159=42240
NAME160=R167
VALUE160=42753
NAME161=R178
VALUE161=45568
NAME162=R180
VALUE162=46080
NAME163=R181
VALUE163=46336
NAME164=R182
VALUE164=46592
NAME165=R183
VALUE165=46848
NAME166=R184
VALUE166=47104
NAME167=R185
VALUE167=47365
NAME168=R186
VALUE168=47624
NAME169=R187
VALUE169=47872
NAME170=R188
VALUE170=48128
NAME171=R189
VALUE171=48384
NAME172=R190
VALUE172=48684
NAME173=R191
VALUE173=48896
NAME174=R192
VALUE174=49264
NAME175=R193
VALUE175=49432
NAME176=R194
VALUE176=49664
NAME177=R195
VALUE177=49920
NAME178=R196
VALUE178=50176
NAME179=R197
VALUE179=50461
NAME180=R198
VALUE180=50688
NAME181=R199
VALUE181=50944
NAME182=R200
VALUE182=51229
NAME183=R201
VALUE183=51456
NAME184=R202
VALUE184=51712
NAME185=R203
VALUE185=51968
NAME186=R204
VALUE186=52245
NAME187=R205
VALUE187=52480
NAME188=R206
VALUE188=52736
NAME189=R207
VALUE189=53013
NAME190=R208
VALUE190=53248
NAME191=R209
VALUE191=53524
NAME192=R210
VALUE192=53760
NAME193=R211
VALUE193=54038
NAME194=R212
VALUE194=54272
NAME195=R213
VALUE195=54548
NAME196=R214
VALUE196=54784
NAME197=R215
VALUE197=55062
NAME198=R216
VALUE198=55311
NAME199=R217
VALUE199=55552
NAME200=R218
VALUE200=55808
NAME201=R219
VALUE201=56089
NAME202=R220
VALUE202=56430
NAME203=R221
VALUE203=56576
NAME204=R222
VALUE204=56835
NAME205=R223
VALUE205=57101
NAME206=R224
VALUE206=57415
NAME207=R225
VALUE207=57600
NAME208=R226
VALUE208=57856
NAME209=R227
VALUE209=58137
NAME210=R228
VALUE210=58478
NAME211=R229
VALUE211=58624
NAME212=R230
VALUE212=58883
NAME213=R231
VALUE213=59149
NAME214=R232
VALUE214=59463
NAME215=R233
VALUE215=59664
NAME216=R234
VALUE216=59920
NAME217=R235
VALUE217=60160
NAME218=R236
VALUE218=60455
NAME219=R237
VALUE219=60688
NAME220=R238
VALUE220=60928
NAME221=R239
VALUE221=61185
NAME222=R240
VALUE222=61574
NAME223=R241
VALUE223=61856
NAME224=R242
VALUE224=61952
NAME225=R243
VALUE225=62271
NAME226=R244
VALUE226=62464
NAME227=R249
VALUE227=63777
NAME228=R250
VALUE228=64000
NAME229=R251
VALUE229=64259
NAME230=R252
VALUE230=64557
NAME231=R253
VALUE231=64768
NAME232=R254
VALUE232=65024
NAME233=R255
VALUE233=65280
NAME234=R256
VALUE234=65536
NAME235=R257
VALUE235=65793
NAME236=R258
VALUE236=66048
NAME237=R259
VALUE237=66304
NAME238=R260
VALUE238=66562
NAME239=R261
VALUE239=66944
NAME240=R262
VALUE240=67072
NAME241=R263
VALUE241=67357
NAME242=R264
VALUE242=67789
NAME243=R265
VALUE243=67941
NAME244=R266
VALUE244=68096
NAME245=R267
VALUE245=68512
NAME246=R268
VALUE246=68612
NAME247=R269
VALUE247=68864
NAME248=R270
VALUE248=69122
NAME249=R271
VALUE249=69415
NAME250=R272
VALUE250=69632
NAME251=R273
VALUE251=69888
NAME252=R274
VALUE252=70144
NAME253=R275
VALUE253=70418
NAME254=R276
VALUE254=70674
NAME255=R277
VALUE255=70930
NAME256=R278
VALUE256=71173
NAME257=R279
VALUE257=71429
NAME258=R280
VALUE258=71685
NAME259=R281
VALUE259=71937
NAME260=R282
VALUE260=72193
NAME261=R283
VALUE261=72449
NAME262=R284
VALUE262=72734
NAME263=R285
VALUE263=72990
NAME264=R286
VALUE264=73216
NAME265=R287
VALUE265=73472
NAME266=R288
VALUE266=73728
NAME267=R289
VALUE267=73984
NAME268=R290
VALUE268=74243
NAME269=R291
VALUE269=74725
NAME270=R292
VALUE270=74761
NAME271=R293
VALUE271=75009
NAME272=R294
VALUE272=75264
NAME273=R295
VALUE273=75564
NAME274=R296
VALUE274=75789
NAME275=R297
VALUE275=76045
NAME276=R298
VALUE276=76301
NAME277=R299
VALUE277=76545
NAME278=R300
VALUE278=76800
NAME279=R301
VALUE279=77080
NAME280=R302
VALUE280=77343
NAME281=R303
VALUE281=77569
NAME282=R304
VALUE282=77839
NAME283=R305
VALUE283=78080
NAME284=R306
VALUE284=78448
NAME285=R307
VALUE285=78642
NAME286=R308
VALUE286=78957
NAME287=R309
VALUE287=79149
NAME288=R310
VALUE288=79405
NAME289=R311
VALUE289=79661
NAME290=R312
VALUE290=79917
NAME291=R313
VALUE291=80173
NAME292=R314
VALUE292=80639
NAME293=R315
VALUE293=80895
NAME294=R316
VALUE294=81151
NAME295=R317
VALUE295=81407
NAME296=R318
VALUE296=81663
NAME297=R319
VALUE297=81667
NAME298=R320
VALUE298=81920
NAME299=R321
VALUE299=82186
NAME300=R322
VALUE300=82432
NAME301=R323
VALUE301=82688
NAME302=R324
VALUE302=82944
NAME303=R325
VALUE303=83201
NAME304=R326
VALUE304=83456
NAME305=R327
VALUE305=83870
NAME306=R328
VALUE306=84210
NAME307=R329
VALUE307=84251
NAME308=R330
VALUE308=84480
NAME309=R331
VALUE309=84836
NAME310=R332
VALUE310=84992
NAME311=R333
VALUE311=85248
NAME312=R334
VALUE312=85748
NAME313=R335
VALUE313=85796
NAME314=R336
VALUE314=86016
NAME315=R337
VALUE315=86430
NAME316=R338
VALUE316=86770
NAME317=R339
VALUE317=86811
NAME318=R340
VALUE318=87040
NAME319=R341
VALUE319=87296
NAME320=R342
VALUE320=87552
NAME321=R343
VALUE321=87808
NAME322=R344
VALUE322=88064
NAME323=R345
VALUE323=88320
NAME324=R346
VALUE324=88578
NAME325=R347
VALUE325=88832
NAME326=R348
VALUE326=89088
NAME327=R349
VALUE327=89344
NAME328=R350
VALUE328=89600
NAME329=R351
VALUE329=89856
NAME330=R352
VALUE330=90112
NAME331=R357
VALUE331=91432
NAME332=R367
VALUE332=93992
NAME333=R411
VALUE333=105220
[FLEX]
CH0_PREDRIVER=0
CH1_PREDRIVER=0
CH2_PREDRIVER=0
CH3_PREDRIVER=0
CH4_PREDRIVER=0
CH5_PREDRIVER=0
CH6_PREDRIVER=0
CH7_PREDRIVER=0
DPLL_REF_LOOPCTL_CHG_QUANT_INTG=0
DPLL_REF_MASHSEED=0
DPLL_REF_UNLOCKDET_CNTSTRT=0
DPLL_REF_UNLOCKDET_CNTSTRT_MSB_6=0
DPLL_REF_UNLOCKDET_VCO_CNTSTRT=0
DPLL_REF_UNLOCKDET_VCO_CNTSTRT_MSB_22=0
MUTE_DPLL_FRLOCK=0
OUT0_freq=156.25 MHz
OUT1_freq=156.25 MHz
OUT2_freq=156.25 MHz
OUT3_freq=156.25 MHz
OUT4_freq=156.25 MHz
OUT5_freq=156.25 MHz
OUT6_freq=156.25 MHz
OUT7_freq=8.0 MHz
PLL1_BAW_CAPDAC=0
PLL1_CP_TRIM=0
PLL1_VCBO_VAR2CON=0
PRIREFBUFGAIN=0
SECREFBUFGAIN=0
TARGET_ADDR_GPIO1_SW=0
VCO1_freq=2500
VCO2_freq=5904
XO_freq=12.8
bFindAddressBtn=Find I2C Addr
i2cAddr=0
sTDC_freq=10.0 Hz
btn_page0_next=NEXT>
combo_backward_compatible=0
combo_dpll_mode=0
matlab_runtime_url=www.mathworks.com/.../matlab-runtime.html
btn_page1_back=<BACK
btn_page1_next=NEXT>
btn_xo_show_instructions=Show Instructions
sXO_freq=12800000
s_wizard_XO_message_box=XO frequency set successfully!\n\nInteger boundary spur = 8.8 MHz\n\nXO R divider = 1\nXO doubler is enabled\nPFD frequency = 25.6 MHz
OUT0_freq=156.25 MHz
OUT1_freq=156.25 MHz
OUT2_freq=156.25 MHz
OUT3_freq=156.25 MHz
OUT4_freq=156.25 MHz
OUT5_freq=156.25 MHz
OUT6_freq=156.25 MHz
OUT7_freq=8.0 MHz
PLL1_RDIV_StaticText=PLL2 R divider (two stages)
bCALC_FREQPLAN=Calculate Frequency Plan
btn_freq_plan_show_instructions=Show Instructions
btn_frequency_plan_apply_solution=Apply selected solution
btn_page2_back=<BACK
btn_page2_next=NEXT>
cb_allow_PLL2_prescaler_of_2=0
cb_manual_override_pll2_rdiv=0
sCH0_1_IN_freq=
sCH0_1_MUX=N/A
sCH2_3_IN_freq=
sCH2_3_MUX=N/A
sCH4_IN_freq=
sCH4_MUX=N/A
sCH5_IN_freq=
sCH5_MUX=N/A
sCH6_IN_freq=
sCH6_MUX=N/A
sCH7_IN_freq=8000000
sCH7_MUX=APLL2
s_wizard_freqplan_message_box=Frequency plan completed!\n\nSelected frequency plan:\n\nVCO1 frequency = 2500.0 MHz\nVCO2 frequency = 5904.0 MHz\n\nAPLL1 settings:\n\nPFD freq = 25600000 Hz\nN divider = 97\nNumerator = 721554505728\nDenominator = 1099511627776\nPost divider = 1\n\nAPLL2 settings:\n\nAPLL2 reference source is VCO1\nPFD freq = 1250000000/9 Hz\nN divider = 42\nNumerator = 31800\nDenominator = 62500\nPost divider 1 = 3\nPost divider 2 = 3
table_frequency_plan_pll1=0
table_frequency_plan_pll2=0
btn_page3_back=<BACK
btn_page3_next=NEXT>
btn_refclk_show_instructions=Show Instructions
cb_enable_PRIREF=1
cb_enable_SECREF=0
combo_PRIREF_BUF_TYPE=2
combo_SECREF_BUF_TYPE=2
combo_ref_priority=0
refclk_pin_select=
sPRIREF_freq=10
sSECREF_freq=
s_wizard_refclk_message_box=INSTRUCTIONS:\n\n1. Enable or disable PRIREF and SECREF as needed. If DPLL is not used, then disable both references and skip this page.\n\n2. Type the frequencies of PRIREF and / or SECREF in Hz. Example frequency formats:\n\n1\n25e6\n100e6 / 3\n\n3. Select interface type. AC or DC buffer is auto-seletected based on reference frequency. If reference frequency is below 5 MHz, then use DC buffer. Otherwise, use AC buffer. To select interface types for AC buffer, refer to the 'Interface Type Selection Tips' in the XO wizard page. The same can be applied to PRIREF and SECREF.\n\n4. Select the input switching mode. The input switching mode is auto-seletected based on the states of PRIREF and SECREF enable. When both references are enabled, then Auto non-revertive is selected. If only one reference is enabled, then manual holdover is selected. However, it is highly recommended to read through the 'Input Switching Mode Selection Guide' in this wizard page and make the decision.\n\n5. If manual fallback or manual holdover is selected, then choose between manually select by register and manually select by REFSEL pin.
btn_page4_back=<BACK
btn_page4_next=NEXT>
btn_ref_validation_show_instructions=Show Instructions
sPRIREF_ACCURACY_PPM=10
sPRIREF_AVG_COUNT=2
sPRIREF_EARLY_MARGIN=1
sPRIREF_EARLY_calc=n/a
sPRIREF_LATE=0
sPRIREF_LATE_MARGIN=1
sPRIREF_LATE_calc=n/a
sPRIREF_PH_VALID_calc=2.46 us
sPRIREF_PPM_INVALID=110
sPRIREF_PPM_TIMER=n/a
sPRIREF_PPM_VALID=100
sSECREF_ACCURACY_PPM=10
sSECREF_AVG_COUNT=2
sSECREF_EARLY_MARGIN=1
sSECREF_EARLY_calc=n/a
sSECREF_LATE=0
sSECREF_LATE_MARGIN=1
sSECREF_LATE_calc=n/a
sSECREF_PH_VALID_calc=n/a
sSECREF_PPM_INVALID=110
sSECREF_PPM_TIMER=n/a
sSECREF_PPM_VALID=100
s_wizard_reference_validation_message_box=INSTRUCTIONS:\n\nIf DPLL is disabled, then skip this page. All reference validation methods have been enabled or disabled automatically based on reference frequency and interface type. However, it is highly recommended to read through the instructions and loose or tighten the thresholds according to application needs.\n\nFrequency detection and early / late window detection are only valid for reference frequencies >= 2 kHz. 1-pps phase detector is only valid for reference frequencies < 2 kHz. For 1-pps input, only enable the 1-pps phase detector and disable all other detectors.\n\n1. Validation timer. The reference must stay valid for 'validation timer' amount of time before it's considered valid. It is recommended to set the validation timer to more than twice of the total reference validation measurement time. The frequency detection measurement time is displayed on the wizard. Measurement time of amplitude detection, early / late clock detection as well as 1-pps phase detection is roughly one cycle of reference clock. Therefore, if the reference frequency is >= 2 kHz, total measurement time is approximately the frequency detection measurement time. If the reference frequency is < 2 kHz, total measuremnet time is approximately 1 cycle of reference clock.\n\n2. Amplitude detector. There are two modes: amplitude detector mode and CMOS slew rate detector mode. In amplitude detector mode, the reference is considered valid if the signal swing is higher than the selected threshold. In CMOS slew rate detector mode, the detection method can be either slew rate detection or VIH / VIL detection. For slew rate detection, the input slew rate must be faster than 0.2 V/ns. For VIH / VIL detection, the input high level must be above 1.8 V and the low level must be below 0.6 V. The amplitude detection mode cannot be used for reference frequencies less than 5 MHz. If the reference frequency is above 5 MHz, then amplitude detection mode is recommended for differential input and the CMOS slew rate detection mode is recommended for single-ended input. If the input swing is too low (for example, the LVDS voltage swing is 400 mV, very marginal compared to the mininum threshold of amplitude detection mode), then amplitude detector can be disabled.\n\n3. Frequency detector. This detector is only valid for PRIREF / SECREF frequencies >= 2 kHz. Frequency detection needs 4 parameters: valid threshold in ppm, invalid threshold in ppm, accuracy in ppm and average count. The PRIREF or SECREF is considered valid if the frequency error between PRIREF / SECREF and XO is within the valid threshold. While it's frequency valid, it's considered as frequency invalid if the frequency error exceeds the invalid threshold. The accuracy in ppm indicates how accurate the valid and invalid threshold can be. In other words, this is the resolution of valid and invalid threshold counters. The minimum average count is 2. Keep it as 2 unless the reference clock has too much wander and the DPLL loop bandwidth is too narrow. In that case, raise the average count to no more than 10. As mentioned, the '0-error' reference for frequency detection is the XO. In reality, of course, the XO frequency is not '0-error'. Therefore, the valid and invalid thresholds must take the XO ppm error into account. The minimum valid threshold should be max XO frequency error + max PRIREF / SECREF frequency error + accuracy in ppm. The minimum invalid threshold should be valid threshold + accuracy in ppm.\n\n4. Early and late clock window detector. This detector is only valid for PRIREF / SECREF frequencies >= 2 kHz. 3 parameters are needed: early counter, late counter and number of missing clocks. After setting early and late counters, the T_early and T_late are calculated accordingly. As shown in the timing diagram, the PRIREF / SECREF is considered valid if its next clock edge falls within ideal next edge - T_early and ideal next edge + T_late. Setting the number of missing clocks to x is equivalent to adding x * reference_clock_period to T_late. So the number of missing clocks is typically set to 0 unless gapped clock needs to be supported. The early and late clock detector uses divided down BAW VCO frequency as its '0-error' reference. However, since this is a very coarse detection method (resolution of T_early and T_late counter is roughly 1.6 ns), the ppm error of the BAW VCO itself is not of concern.\n\n5. 1-pps phase detector. This detector is only valid for PRIREF / SECREF frequencies < 2 kHz. T_jitter is auto-calculated according to the phase detector counter. As shown in the timing diagram, the PRIREF / SECREF is considered valid if the next clock edge falls within ideal next edge - T_jitter and ideal next edge + T_jitter. Note that the '0-error' clock reference for 1-pps phase detector is the XO, so T_jitter must be greater than the sum of: (1) XO phase error accumulated through one PRIREF / SECREF clock period (for example, 1 second for 1-pps input). This includes the phase error caused by frequency inaccuracy, accumulated jitter as well as wander. (2) The max period jitter of PRIREF / SECREF. Therefore, low frequency and high stability XO is recommended for 1-pps input. This is because for XOs with the same frequency stability, the one with the lower frequency accumulates less phase error over fixed period of time. 12.8 MHz TCXO / OCXO is recommended for 1-pps input.
DPLL_VCO_freq=2500
bRUN_SCRIPT=Run Script
btn_dpll_show_instructions=Show Instructions
btn_page5_back=<BACK
btn_page5_next=NEXT>
btn_restore_dpll_reg=Restore Calculated DPLL Settings
cb_show_dpll_registers=0
combo_disable_fastlock=1
combo_set_max_tdc_freq=0
combo_switching_method=0
sDPLL_LBW=0.01
sDPLL_LBW_ACT=0.0101
sDPLL_PEAK=0.1
sDPLL_PEAK_ERROR=1
sMAX_TDC_freq=26000000
sPRIREF_freq_display=10.0 Hz
sSECREF_freq_display=Disabled
sTDC_freq=10.0 Hz
s_wizard_dpll_message_box=DPLL calculation completed!\n\nTDC frequency = 10\n\nPlanned VCO1 frequency = 2500000000\nActual VCO1 frequency = 2500000000\nPLL1 frequency error = 0 ppb\n\nPlanned VCO2 frequency = 5904000000\nActual VCO2 frequency = 5904000000\nPLL2 frequency error = 0 ppb\n\nDPLL fastlock time = 0.00 fs + 0.00 fs = 0.00 fs\n\nTotal DPLL frequency lock time ~= DPLL fastlock time + 2 * DPLL frequency lock measurement time\n\nTotal DPLL phase lock time ~= DPLL fastlock time + 2 * DPLL phase lock measurement time
BAW_LOCK_PPM_THRESH=5
BAW_UNLK_PPM_THRESH=10
DPLL_PL_LOCK_calc=371.69 ps
DPLL_PL_UNLK_calc=47.58 ns
btn_baw_lock_detect_default=Set Default
btn_dpll2_show_instructions=Show Instructions
btn_dpll_freq_lock_detect_default=Set Default
btn_history_recommend=Min Values Required
btn_page6_back=<BACK
btn_page6_next=NEXT>
btn_ph_threshold_recommend=Recommended
sBAW_LOCK_ACCURACY_PPM=1
sBAW_LOCK_AVG=2
sBAW_TMEAS_LOCK_calc=19.2000 ms
sDPLL_HISTCNT_calc=26.21 ks
sDPLL_HISTDLY_calc=4.61 ks
sDPLL_LOCK_ACCURACY_PPM=1
sDPLL_LOCK_AVG=10
sDPLL_LOCK_PPM=1
sDPLL_PL_MEAS_TIME=99.01 s
sDPLL_TMEAS_LOCK_calc=100.0000 ms
sDPLL_UNLK_PPM=10
s_wizard_dpll2_message_box=INSTRUCTIONS:\n\nAll lock detect settings are set to either default or recommended values after the DPLL script is run. Still, it is highly recommended to go through the instructions and make the adjustments.\n\n1. BAW frequency lock detect. Disable this if DPLL is enabled. This detector is only useful if the DPLL is disabled and the device works in free-running mode. Enter lock threshold in ppm, unlock threshold in ppm, average count (min value = 2) and accuracy in ppm. The BAW (VCO1) is considered to be locked if the frequency error between the BAW and the XO is within lock threshold. Once the BAW is locked, it's considered to be unlocked if the frequency error exceeds the unlock threshold. The step size of lock and unlock threshold in ppm = accuracy / average. If there's no specific requirement for BAW lock detect, click 'Set Default'.\n\n2. DPLL frequency lock detect. Enter lock and unlock thresholds in ppm, average count (min value = 2) as well as accuracy in ppm. The DPLL is considered to be frequency locked if the frequency error between the VCO1 and the references is within the lock threshold. While the DPLL is frequency locked, it's considered to be frequency unlocked if the frequency error exceeds the unlock threshold. The step size of lock and unlock threshold = accuracy / average. If there's no specific requirement for DPLL frequency lock detect, click 'Set Default'.\n\n3. DPLL phase lock detect. Set lock and unlock threshold counters. The actual lock and unlock thresholds in second are then calculated accordingly. The DPLL is considered as phase locked if the phase difference between the two inputs of TDC (divided reference and divided VCO1) is within the lock threshold. While the DPLL is phase locked, it's considered as phase unlocked if the phase difference exceeds the unlock threshold. Use recommended values for this. The lock and unlock counters should not be manually set, and they are only used for engineering debugging purposes.\n\n4. Tuning word history. This block sets the tuning word history for holdover. Set history counter and delay counter. The averaging time and delay time are then auto-calculated. Refer to datasheet section '9.3.7.4 Tuning Word History' for details. If there's no specific requirement for holdover tuning word, click 'Min Values Required'. This makes sure that the delay time is more than 8 times of the reference frequency validation measurement time, and that the averaging time is longer than the delay time.
btn_page7_back=<BACK
PLL1_24b_DEN=0
PLL1_24b_NUM=43008
PLL1_DEN=1099511627776
PLL1_PFD_freq=25.6
VCO1_freq=2500
XO_freq=12.8
PLL2_DEN_fixed=16777216
PLL2_PFD_freq=138.8888888889
VCO1_freq=2500
VCO2_freq=5904
XO_freq=12.8
MUTE_DPLL_FRLOCK=0
OUT0_freq=156.25 MHz
OUT1_freq=156.25 MHz
OUT2_freq=156.25 MHz
OUT3_freq=156.25 MHz
OUT4_freq=156.25 MHz
OUT5_freq=156.25 MHz
OUT6_freq=156.25 MHz
OUT7_freq=8.0 MHz
PLL2PDIV1_freq=1968
PLL2PDIV2_freq=1968
VCO1_freq=2500
VCO2_freq=5904
sOUT7_DIV=246
AbsDCO_ppb_error=0.01
DPLL_DCO_FREQ_PPB_ACT=0
DPLL_DCO_STEP_ACT=0
DPLL_REF_NUM_calculated=194031463725
bDPLL_FDECR=Decrement
bDPLL_FINCR=Increment
bResetNumerator0ppb=Reload Original DPLL Numerator
cbDCO_MODE=1
sDPLL_DCO_STEP=0.01
bReadStatus=Read Status
bClearAllFlagStickyStatus=Clear All Flags
txtNVMSCRC=0x3B
txtNVMCNT=0x01
valEEREV=0
valNVM_SPARE_BY1=0
valNVM_SPARE_BY0=0
valNVM_SPARE_BY2=0
valNVM_SPARE_BY3=0
cmbI2C_ADDR=0
btnEE_READSTATUS=Read EEPROM Status
btnEE_TICS2SEQ=Export EEPROM Sequence
btnEE_TICS2EPR=Export EEPROM Map
btnEE_TICS2DUT=Program EEPROM
btnEE_DUT2TICS=Read Extra EEPROM Bytes
cmbSEL_EXTRA_EE_BYTES=0
txtNVMLCRC=0x00
txtNVMCRCERR=0
txtNVMBUSY=0
val_EE_DUMP=
