TICSPRO-SW: LMK04832 PLL2 not locking after loading setup from newer TICS-Pro Version

I have two guesses what could be happening:

• Something about modern TICS Pro versions is writing PLL2_N and PLL2_N_CAL, such that the calibration LSBs are being written at the wrong moment. TICS Pro logs all of the register writes to the C:\Program Files (x86)\Texas Instruments\TICS Pro\log00x.txt file, where x ∈ (0, 1). You could review these logs (if there's other device history present, you can delete the logs for a fresh log) and sort out in what order PLL2_N and PLL2_N_CAL values are being written. PLL2_N_CAL should always be written before PLL2_N, and PLL2_N should be written after all other PLL-related registers, with the LSB register being written last. I'm also happy to take a look at the logs to check.
• The decreased loading time is resulting in faster writes, so the calibration routine is beginning before some circuit block is fully powered up, leading to incorrect results. If this is the case, we need to insert a small delay before the calibrating PLL2_N write. If we rule out a write order-based explanation, I can try putting together a post-write hook that re-writes PLL2_N LSBs after a few ms delay to allow power rails to settle.

I've tried replicating the issue on my end and I'm not seeing it. The issue might be related to loop bandwidth, or it might be something specific to a TCS/hex file you're using. If you can share the config, I can try to replicate the issue with that specific config.

Hello derek,

my collegue found out, that there is a wrong register value stored in the .tcs file.

Herer is his answer

One error was in saved .tcs files. I have corrected one file and the two PLLs lock after the file load.
It was first "Settings_LMK04832_SyncEN_Pll1Pll2_DLD_1SHOT_PLL1_R25_PLL2_div_sync_DZM_clkout8_Nested_Reclockt_NoSYSREF_PD_SYNC_DISSYSREF_CLKout2_500MHz_HO19_Test.tcs"
 File loaded with Tics Pro. On picture 2 a line is marked where wrong data
 09 was written to LMK04832 register 0x167. Figure 1 shows LMK registers which are used for
 N parts of PLL2.  On the left column I have shown faulty lines from the above .tcs file. This leads to
 that in PLL2 divider N wrong data was written and therefore PLL2 does not lock.
 In our case N = 50 should be.
I have corrected the .tcs file with the values from the right column and in a new file: "MK04832_SyncEN_Pll1Pll2_DLD_1SHOT_PLL1_R25_PLL2_div_sync_DZM_clkout8_Nested_Reclockt_NoSYSREF_PD_SYNC_DISSYSREF_CLKout2_500MHz_HO19_R389_corr_Test.tcs".
 Now after loading the corrected file PLL2 locks immediately.

---Wrong          ---Correct
NAME122=R389       NAME122=R389 
VALUE122=91913     VALUE122=91904 
---in HEX          --in HEX 
VALUE122=0x16709   VALUE122=0x16700 

I will also send you two .tcs files. One is originsle file: "Settings_LMK04832_SyncEN_Pll1Pll2_DLD_1SHOT_PLL1_R25_PLL2_div_sync_DZM_clkout8_Nested_Reclockt_NoSYSREF_PD_SYNC_DISSYSREF_CLKout2_500MHz_HO19_Test.tcs"
which was saved by Tics Pro and another file that I corrected manually: "Settings_LMK04832_SyncEN_Pll1Pll2_DLD_1SHOT_PLL1_R25_PLL2_div_sync_DZM_clkout8_Nested_Reclockt_NoSYSREF_PD_SYNC_DISSYSREF_CLKout2_500MHz_HO19_R389_corr_Test.tcs"
I think this should help with troubleshooting in Tics Pro software.
After loading these .tcs files, three synchronized 25MHz, 250MHz and 500MHz will be displayed from 25MHz ClkIn0 signal. 25 MHz output was used as nested 0-delay feedback signal.

Regards,

Hendrik

Settings_LMK04832_SyncEN_Pll1Pll2_DLD_1SHOT_PLL1_R25_PLL2_div_sync_DZM_clkout8_Nested_Reclockt_NoSYSREF_PD_SYNC_DISSYSREF_CLKout2_500MHz_HO19_Test.tcsSettings_LMK04832_SyncEN_Pll1Pll2_DLD_1SHOT_PLL1_R25_PLL2_div_sync_DZM_clkout8_Nested_Reclockt_NoSYSREF_PD_SYNC_DISSYSREF_CLKout2_500MHz_HO19_R389_corr_Test.tcs