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LMK62I0-100M: jitter specification check

Tim Peng
Prodigy 40 points
Part Number: LMK62I0-100M
Other Parts Discussed in Thread: LMK6H

Hi Support

We would like to check if jitter specification of LMK62I0-100M could meet PCIe gen6 application. Please help to check. 

Requirements :

1. package size: 5*3.2 mm

2. frequency :  100MHz

3. Jitter:

Please let me know if you need more specification.

  • 0
    TI__Expert 7190 points

    Hi Tim, 

    We have a tool in TICS Pro (which can be found under Tools -> PCIe Report Generator, download link here: https://www.ti.com/tool/TICSPRO-SW) that can calculate RMS jitter after applying PCIe filters to a phase noise plot provided by the user. I did a quick check with a typical 100MHz phase noise plot from LMK62I0-100M and after the PCIe Gen 6 filters have been applied the typical RMS jitter is around 4-7 fs. After including variation over supply voltage, operating temperature, etc. I still expect plenty of margin in performance. 

    If the maximum jitter specification you provided does not include any filtering, then LMK62 may not be able to meet those specifications since we haven't fully characterized the phase noise of this device at 100MHz. If that's the case, I would recommend switching to LMK6H since it has been fully validated to be compliant with PCIe Gen 1-6. Let me know if you have any other questions. 

    Regards, 

    Connor 

  • 0 in reply to Connor Lewis
    Prodigy 40 points

    Hi Connor, 

    Could you please help to walk me through the procedure how to generate such jitter result? I have downloaded the tool, it looks like I have to input some kind of file? and when you mentioned filtering, did you mean by "integration bandwidth"?

    by the way, thanks for suggestion of LMK6H. However, we have a limitation of reusing existing PCB and footprint is 5*3.2mm. there is no 5*3.2mm option of using LMK6H. 

  • 0 in reply to Connor Lewis
    Prodigy 40 points

    Hi Connor, 

    A few questions, please help to reply. 

    (1) Could you please help to walk me through the procedure how to generate such jitter result? I have downloaded the tool, it looks like I have to input some kind of file?

    (2) and when you mentioned filtering, did you mean by "integration bandwidth"?

    (3) by the way, thanks for suggestion of LMK6H. However, we have a limitation of reusing existing PCB and footprint is 5*3.2mm. there is no 5*3.2mm option of using LMK6H.   Do you think there is a part and the PCB footprint is 5*3.2 mm and verified with PCIe Gen 6 specification? 

  • +1 in reply to Tim Peng
    TI__Expert 7190 points

    Hi Tim, 

    Sorry for the delayed response here. 

    1. Yes, the tool requires a trace of a phase noise plot from a phase noise analyzer. Here's an example test report that describes a bit more about how the PCIe compliance tool works: https://www.ti.com/lit/an/snla445/snla445.pdf 

    2. PCIe reference clocks typically go through a high-pass filter which is defined in the standard of each PCIe generation. In general, the newer PCIe generations have improved filters to reduce more jitter from the reference clock. After filtering, the integration bandwidth is used to calculate RMS jitter. 

    3. The only oscillators we currently offer in the 5x3.2 mm package are the LMK62 family. 

    Let me know if you have any other questions. 

    Regards, 

    Connor 

  • 0 in reply to Connor Lewis
    Prodigy 40 points

    Hi Connor 

    As you replied a few days ago, quoted "I did a quick check with a typical 100MHz phase noise plot from LMK62I0-100M and after the PCIe Gen 6 filters have been applied the typical RMS jitter is around 4-7 fs.". 

    This result looks promising. could you please help to share some snapshots of results?