Other Parts Discussed in Thread: LMX2571
Hello, I am doing some prototyping with the LMX2571 evaluation module. I have the module talking correctly to my TICs pro software and even tested some FSK modes, different PLL settings, and some differing output clock frequencies.
I am finding it difficult to find the correct counter and divide values to get the LMX2571 to achieve lock or have the TICs pro tool autogenerate values for the VCO or divide counters to be within their correct (achievable) range.
My question is - what is the appropriate order of operations when entering values into the TICs PRO or PLLatinum Sim such that the tool selects and auto-fills the counter values within range?
Is there a tutorial on how to use these simulation tools better and to make the appropriate design trade-offs?
By playing around with the tool I have found multiple ways to generate a 389MHz clock through trial and error. Is there a preferred method for downselecting the various PLL settings?
Here are some of my more specific design parameters:
- Generate a clock for 389MHz and 855MHz local oscillator. I have yet to successfully build the 855MHz clock.
- FSK modulation at 333.33 KHz steps.
- Input oscillator at 20MHz, although this can change to find a more ideal setting.
- I am using the LMX2571 in Synthesizer mode (internal PLL and VCO)
