LMK04832-SP: LMK04832-SP

Aside from the global SYSREF_DDLY field which would apply to the entire SYSREF distribution path and every SYSREF output, there is a local analog delay in each channel that can extend the total local SYSREF delay by about 610ps.

If you can accept the SYSREF pulse arriving in several stages (some JESD IP allows for offset by some, or any, number of SYSREF cycles), you could use the SCLKx_y_DIS_MODE and SYSREF_GBL_PD settings, and the dynamic digital delay function, to dynamically realign the SYSREF and mask outputs that are too far out of alignment with each other. Unfortunately I don't think the dynamic digital delay time to shift is always deterministic, or if it is we haven't thoroughly explored this aspect of the device; and I know there are some datasheet notes about dynamic digital delay and the SYSREF_DDLY which make it somewhat challenging to use properly. And this won't work if all SYSREF pulses need to arrive within e.g. 100ns of each other, since the dynamic digital delay and masking operations are register-based, which is limited by the speed of the SPI writes.

You can in principle use multiple independent D-flip-flops clocked with the device clocks at different DCLKx_y_DDLY values, as a retimer for a slower pulsed SYSREF on the D ports. The device clock delay can vary by around 1000 clock distribution path cycles, allowing a much wider total delay variation. But there are a bunch of drawbacks:

• The clock ports need to be independent for each flip-flop, and the only space-grade TI device that I am aware of which exposes clock pins for every flip-flop and comes with more than two channels is SN54LVTH162374-SP, with 16 channels and 48 pins. Depending on how many SYSREFs with large delays are required, it may be better to use two-channel DFFs.
• This solution is limited to outputs that implement LVCMOS (CLKout8, CLKout10, and odd-numbered CLKoutYs), and only generates LVCMOS SYSREF outputs (since the new output source is an LVCMOS DFF). Using three full outputs (CLKout8/9/10 or 9/10/11) for SYSREF, and all remaining available LVCMOS outputs for device clocks, it is possible to generate up to six single-ended LVCMOS re-timed SYSREFs.
• This solution only works below 250MHz, since LVCMOS outputs are not rated for higher frequency. While there isn't a lower limit, the maximum SYSREF deviation is capped at 1023 clock distribution path cycles, since the device clock dividers cannot go higher than 1023.
• There is some unknown latency accumulated in the DFF retimer stage. If other clocks are aligned to these SYSREFs, particularly on other LMK04832-SP devices, calibrating out this latency may be challenging.
• The LVCMOS output propagation delay varies greatly with temperature - several hundred picoseconds across full temperature range is possible.
• You lose the analog delay since you use the device clocks as a re-timer and the device clocks do not have analog delay paths. In light of the latency and propagation delay variation challenges detailed above, this can be troublesome.

So I wouldn't recommend this as my first option - it's a last-resort option for when all else fails. There's probably other, easier solutions before this point, like setting some constant offset of high-frequency clock cycles to shift the SYSREF timing at the target devices. If you're using the SYSREF as some kind of precisely-timed pulse generator, and not for a JESD configuration, the flip-flop retimer solution might be more appropriate.