LMH1983: 1983 Unlock causes the encoded picture to be split up and down and an exception occurs.

Hi Delun, 

Are you using the LMH1983 in default configuration or are you changing any registers using I2C? Also do you have any idea which output clock pin is contributing to the issue?

Best,

Michael Gamota

Hi Michael,

Yes, we are using the LMH1983 in default mode. We cannot determine which clock is faulty (is there such a mechanism?), we can only confirm the status (FPGA) of LMH1983 from the lock pin.

Hi Delun,

Did you use LMH1981? Do you have a valid video signal to LMH1981?

Hi Michael,

No, we did not use LMH1981. H sync, V sync & F sync in LMH1983 were controlled by FPGA.

Hi Delun,

LMH1983 takes the H-sync to lock the VCXO. To debug, check if the H-sync signal is stable and the video format is one of those in Table 2. Use a scope to check the Vtune voltage of the VCXO and check the output frequency of the VCXO. Do a register read back to check the status (Register 0x0, 0x1, 0x2).

Hi Michael,

We have read a register as below (Register 0x0, 0x1, 0x2) when an abnormality occurs on the screen.

Hi Delun,

I cannot understand your read back data format, could you tell me what are the read back values of these registers?

Hi Michael,

We probably know how to read the register value to confirm the PLL status, thank you.

Hi Delun,

Read back tells there is no reference to PLL1; PLL1 is not locked; PLL1 is in holdover status.

Did you check the H-sync signal?