Other Parts Discussed in Thread: CDCE6214
Tool/software:
Hello E2E Experts,
Good day.
June 25, 2024
I am designing a general-purpose bit synchronizer that receives an analog bit
stream of data (typically contaminated with noise) and outputs digital data with
a clock that can be used to sample the digitized data.
The design requires a clock with the following requirements:
1. Frequency range: 100 MHz to 320 MHz
2. Frequency resolution: better than 50 ppm
3. Frequency tracking range: +/- 10%
a. The initial programmed frequency should track changes in the
analog input data rate without any glitches or phase
discontinuities.
b. The rate of the frequency change will be less than
1%/ millisecond.
We are considering the use of the TI CDCE706 with an AD9850 DDS from
Analog Devices. The DDS has very high resolution and can provide a high
quality clock that can be varied, for example, from 6 MHz to 16 MHz.
Frequency tracking will be performed by connecting the CDCE706's clock
input to the DDS's output (note that the AD9850 can output a digital clock).
This will cause the VCO to smoothly track small changes in the DDS
frequency.
The CDCE706 data sheet states that the Normal Speed VCO range is 80
MHz to 200 MHz and that the High Speed VCO range is 180 MHz to 300
MHz. However, note 3 on page 7 states that the VCOs can go lower in
frequency with a degradation of phase noise. Figure 29 on page 33 shows
that the Normal Speed VCO can actually range from less than 60 MHz to
more than 240 MHz and that the High Speed VCO can actually range from
less than 100 MHz to more than 320 MHz. Can these extended ranges be
guaranteed? The degradation in phase noise has no significance for our
application.
Please let me know if the above solution is viable or problematic.
Regards,
CSC
