Tool/software:
Hello，
According to the datasheet, under the condition of fVCO = 6.0 GHz, 100 kHz, the PNVCO should be 110.3 dBc/Hz, but the actual measured value is about 120 dBc/Hz; At fVCO = 10.2 GHz, 100 kHz, the PNVCO should be 105 dBc/Hz, but the actual measured value is around 106-110 dBc/Hz.
Could you help suggest is that within the tolerance？
Thanks a lot,
Suri
Hi Suri,
Do you have the phase noise plot of your reference clock?
In addition, please change the capacitor at pin 41 to 10µF. This would reduce in-band noise. Further noise reduction can be obtained by changing the capacitor at pin 3 to 1µF.
Hi Noel，
Pls check below picfutres for "before and after the attenuator" and the part number of attenuator.
Thanks,
Suri
Hi Suri,
Both the phase noise and slew rate of the reference clock will affect PLL noise.
Now we know phase noise is good, so we need to investigate whether the slew rate is bad, we need a scope to check this out.
Anyway, other than phase noise and slew rate, I don't have other idea why you cannot get the desired performance.
FYI, I did a quick check on the EVM, in-band phase noise at 10GHz should be below -110dBc/Hz.
