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LMX2581E: Long Term Operation

Klaus Schoenwald
Prodigy 10 points
Part Number: LMX2581E
Other Parts Discussed in Thread: CODELOADER

Tool/software:

Hello,

we use the LMX2581E in a Downconverter as Local Oscillator (LO). So far I can initialize the unit and set the frequency and the unit is operating well. The frequency will not changed so much so it could be that the chip will not reveive a new frequency setting over some weeks.

So far so good, now my problem. Sometimes after some days or weeks (without re-programming the frequency) the unit will lost the lock. A re-initialize and/or re-setting of the frequency will solve the problem. However a periodic initializing or re-setting  of the frequency is not so nice since we lost the downconverted signal for a short time.

We have actual 4 prototype boards running and all of them show the same issue, so a expect that this would be a general problem.

We have two chips on each board, one is used in a 

1)  Wideband operation as intereger N configuration 1MHz stepsize from

- 1715MHz – 1900MHz, (3430-3800) VCO 4 divider 2

- 1900MHz – 2270MHz, VCO 1

- 2270MHz – 2720MHz, VCO 2

- 2720MHz – 3215MHz, VCO 3

2) Small band operation as fractional-N configuration 1khz stepsize from

- 695,04091MHz – 695,95000MHz (2780.16364-2783.8) , VCO 3 divider 4

So far we see the lock problem only in 1) wideband operation synthesizer.

Please find attache the schematic of synthesizer 1). OSC in = 50MHz

and the Settings of the register.

#define LO1_R5INIT      0x40870010  // Reset Chip to default settings, default from codeloader TI
#define LO1_R15         0x021FE80F  // default from codeloader TI
#define LO1_R13         0x4082C10D  // default from codeloader TI
#define LO1_R10         0x210050CA  // default from docu TI
#define LO1_R9          0x03C7C039  // default from docu TI
#define LO1_R8          0x207DDBF8  // default from docu TI
#define LO1_R7          0x00000317  // default from codeloader TI
#define LO1_R6          0x000004C6  // default from codeloader TI

#define LO1_R5            0x00108005  // 0x00r08d05 d=0 OutputA is the VCO; r=1 fref<64MHz
#define LO1_R5DIV         0x00108805  // 0x00r08d05 d=8 OutputA Divider active, is set in R3 to 2; r=1 fref<64MHz
#define LO1_R4            0x00000004  // default from codeloader TI
#define LO1_R3            0x200002B3  // 0x20000gg3 gg = gain(0..47)*4+3; -2dB = 10*4+3 = 43 = 0x2B (Output PWR Off)
#define LO1_R2            0x0C000002  // 0x0Cddddd2 ddddd = PLL_DEN = 0 = 0x0000
#define LO1_R1            0xFE000321  // 0xFE000rr1 rr = RefDiv = 0x32 = 50 (VCO 4 Selected)
#define LO1_R0            0x68DA0000  // 0x6mmm0000 mmm = freq from 1880MHz to 3880MHz; default = 2266 = 0x8DA
                                      // default for RFin = 1500MHz = LO= int(1500 + 765.5 + 0.5)  == 2266 = 0x8DA

Is there are any recommandation, to improve that?

Best Regards

Klaus Schoenwald

  • 0
    TI__Guru** 107450 points

    We will check in next week.

  • 0 in reply to Noel Fung
    TI__Guru** 107450 points

    Hi Klaus,

    Looks like this is a loop filter issue.

    In wideband operation, fpd = 1MHz, loop bandwidth is 1.6kHz and phase margin is 11deg, so the loop is not stable. 

    You can change R42 to 3.3kΩ, this will increase the loop bandwidth to 2.98kHz and phase margin to 57deg. 

    In small band operation, what is the fpd? Same loop filter?

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Hi Noel,

    thanks for your help.

    for the small band operation I used

    LO2_R1            0x4E013011  // 0x4Emm3rr1 mm = PLL_Num bit12.. = 0x02 = 8192 -> 0x01; RefDiv = 0x01 = 1

    The settings I used calculated from the CODELOADER Tool for fpd 900uA.

    The Loop Filter is the same setup as the wideband.

    After a look to the documentation Loop Gain is CPG[4:0]*110uA, so the loop gain will be always higher as Codeloader calculates. What is correct?

    Please find attched the calculation for loop bandwidth and phase margin for both configuration (claculatetd with the TI-Toolset Platinium Sim), the values are differs to yours, what did I wrong?

    Wideband Band Operation (Sample at Center Frequency 2266MHz):

    Phase Margin is still to small, but not as small as your calculation. What is wrong?

    Small Band Operation:

    Should be Ok, or?

    Best Regards

    Klaus

  • 0 in reply to Klaus Schoenwald
    TI__Guru** 107450 points

    Hi Klaus,

    I set the wrong charge pump current, your sim result is correct. In PLL Sim, we can type the value in the Kpd box to make it same as CodeLoader value.

    Anyway, with 1MHz fpd, phase margin is not high enough. Set R42 to 1kΩ seems to work in both configurations.