LMK04832: Output Synchronization: DCLK and SDCLK

KLN

Part Number: LMK04832

Tool/software:

Hi Team,

We are using LMK04832 in one of our design, we are trying to synchronize the LMK Outputs i.e., DCLK and SDCLK synch.

We are trying to write the following register for sync, but we do not observe DCLK and SDCLK synched. i,e., observed both on oscilloscope, observing around 2.5ns constant delay from power on to power on.

# For Sync divider reset following wrote.

0x0144FF
0x013903

Onboard, SDCLK and DCLK are length matched

Attached the lmk config file.

Fullscreen 1p350g_168p75m_v5.txt Download

R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000670
R12	0x000C51
R13	0x000D04
R256	0x010012
R257	0x01010A
R258	0x0102F0
R259	0x010344
R260	0x010420
R261	0x010500
R262	0x010601
R263	0x010700
R264	0x010812
R265	0x01090A
R266	0x010A10
R267	0x010B44
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F35
R272	0x011012
R273	0x01110A
R274	0x011210
R275	0x011344
R276	0x011420
R277	0x011500
R278	0x011601
R279	0x011715
R280	0x011812
R281	0x01190A
R282	0x011A10
R283	0x011B44
R284	0x011C20
R285	0x011D00
R286	0x011E01
R287	0x011F01
R288	0x012012
R289	0x01210A
R290	0x012210
R291	0x012344
R292	0x012420
R293	0x012500
R294	0x012601
R295	0x012755
R296	0x012808
R297	0x01290A
R298	0x012A90
R299	0x012B40
R300	0x012C10
R301	0x012D00
R302	0x012E01
R303	0x012F00
R304	0x013011
R305	0x01310A
R306	0x013290
R307	0x013344
R308	0x013420
R309	0x013500
R310	0x013601
R311	0x013705
R312	0x013825
R313	0x013903
R314	0x013A03
R315	0x013B84
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F2B
R320	0x01400B
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x014400
R325	0x014500
R326	0x014608
R327	0x01470A
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015408
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A87
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F0B
R352	0x016000
R353	0x016110
R354	0x016264
R355	0x016300
R356	0x016400
R357	0x0165A2
R358	0x016600
R359	0x016700
R361	0x016958
R362	0x016A20
R363	0x016B00
R366	0x016E13
R371	0x017310
R375	0x017700
R386	0x018200
R387	0x018300
R388	0x018480
R389	0x018500
R392	0x018800
R360	0x01681B
R1365	0x055500

Please look into this.

Thanks

over 1 year ago

0 vicente flores prado over 1 year ago

TI__Mastermind 32152 points

Hi KLM,

Give us until the end of the week to look into this.

Beat regards,

Vicente

0 KLN over 1 year ago in reply to vicente flores prado

Intellectual 320 points

Sure

0 vicente flores prado over 1 year ago in reply to KLN

TI__Mastermind 32152 points

Hi KLN,
Just to ensure I understand - are you getting the same phase every time after sync?
Or are you saying the phase is randomized after sync?
If possible, always attach a .tcs file.

Best regards,

Vicente

0 KLN over 1 year ago in reply to vicente flores prado

Intellectual 320 points

phase is constant power on to power on.

but not aligned

0 vicente flores prado over 1 year ago in reply to KLN

TI__Mastermind 32152 points

Hello KLN,
But are you performing SYNC event after every power cycle?
I am curious - upon power up if you change the output divider values to randomize the phase and switch to the output divider value you need & SYNC again - will the phase be the same or deterministic?

Best regards,

Vicente

0 KLN over 1 year ago in reply to vicente flores prado

Intellectual 320 points

Hi,

We are using SYNC PIN

We are using this registers to write

0x0144FF
0x013903

vicente flores prado said:
I am curious - upon power up if you change the output divider values to randomize the phase and switch to the output divider value you need & SYNC again - will the phase be the same or deterministic?

Is this recommended way? you simply want to try out?

Phase/delay is constant but not aligned with each other

0 vicente flores prado over 1 year ago in reply to KLN

TI__Mastermind 32152 points

Hi KLN,

Yes this is the recommended way.

Sync results in deterministic phase.

its possible due to skew that you don’t have edge aligned outputs every time but you can use delays to account for this and get edge aligned outputs every time.

if you’re performing a sync event and witness the phase become the same or deterministic - the feature is working as expected.

best regards,

vicente

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LMK04832: Output Synchronization: DCLK and SDCLK