Tool/software:
Hi, we're looking at producing the CDCE6214-Q1 with a VCTCXO; unfortunately all of the oscillators that are suitably well stocked have single-ended peak-to-peak (clipped sinewave) output voltages of only 0.8V which doesn't meet the requirement when using it as an LVCMOS input.
We're currently looking at three possible solutions:
1. Throw an op-amp / level-shifter / buffer between the oscillator and clock generator; we'd like to avoid this if possible just to reduce part count, failure modes, etc.
2. Configure the input (let's say primary) as LVDS, float the PRIREF_N pin so that the internal biasing network can bias it to 1.65V, and then take advantage of the 0.4V swing requirement of the LVDS input mode with the 0.8Vpp. We're yet to try to simulate this so we're not certain it'd work, and if it did, how reliable it'd be.
3. Feed the oscillator to SECREF_N and configure the secondary reference input for use with a XTAL. This apparently worked on the older CDCE9xx clock generator but we're not sure if it will work on the CDCE6214-Q1.
Does anyone have experience hooking up this kind of weak oscillator to this particular clock generator? If we can go with option #3 that'd be ideal, so if anyone has advice or experience in that approach we'd appreciate hearing from you.
Cheers,
Joshua
