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Original question:

LMK03806: Programming LMK03806 and others

LMK03318: Several questions on LMK03318 and LMK03318-EVM

Prasoon Joshi
Prodigy 90 points
Part Number: LMK03318

Tool/software:

Hi,

I have a few questions regarding LMK03318 and the evaluation board:

  1. Does VDDO for the clock outputs need to be 1.8V for LVCMOS? Or, will the output be automatically on 1.8V even if VDDO is 3.3V? I plan to have some outputs be 3.3V LVPECL and some outputs be LVCMOS.
  2. Is it recommended to have separate bypassing for the different output banks? I think the EVM does it this way.
  3. On the EVM there are several instances of 0 Ohm resistors. Does the LMK need them, or, are the 0Ohms present for disabling something on the board, if needed?
  4. If I need to disable an output on the fly, can the power to the VDDO for that output be disabled? I am looking for a way to avoid re-programming to disable an output.
  5. Is the momentary push button on GPIO0 on the EVM for the output sync capability?
  6. Are ferrite beads needed on the LDOs for VDD and VDDO as implemented on the EVM?

Thanks,

Prasoon

  • +1
    TI__Expert 4315 points

    Prasoon,

    1. The LVCMOS outputs will be 1.8V regardless of VDDO, however it is recommended to have the corresponding VDDO have 1.8V, if possible. If 3.3V LVCMOS outputs are needed, the STATUS pins can be used for that case.

    2. A ferrite bead and bulk cap may be shared to supply multiple output banks with the same PLL/frequency. But we recommend each VDDO pin should have its own bypass cap.

    3. Many of these 0 ohm resistors are placed to allow for more customization ability for the EVM.

    4. The EVM has jumpers that can be populated and used for this [JP9-14] 

    5. Yes

    6. Overall, yes, but see my answer to question 2.