LMX2820: jitter degradation vs f_pfd

Hi Samuel,

The main drawback of using a low input clock freq, as you know, fpd is also low. As a result, N-divider becomes big. This increases the PLL noise by 20log(N). You cannot enjoy the low FOM of the LMX2820 device.

The other downside of using low input clock freq is that, if it is a sine wave clock, slew rate of the clock is bad and this in turn hurt the PLL noise.

The last problem with low input clock freq is, your loop bandwidth cannot be high. Therefore, you cannot use the loop filter to suppress inband VCO noise. 

You can use PLL Sim (https://www.ti.com/tool/PLLATINUMSIM-SW) to estimate the overall phase noise difference between these two configurations. 

Hello Noel,

In the two examples, the input clock is not really that low: oscin_p/n= 640_MHz.

The max for oscin_p/n is 1400_MHz.

But, the pfd frequency is fairly low in example 1, 10MHz, versus 320MHz in example 2.

For example 1, feedback_divider=1007, so 20*log(1007)=60.060589_dB increase in PLL noise.

> The last problem with low input clock freq is, your loop bandwidth cannot be high.

>  Therefore, you cannot use the loop filter to suppress inband VCO noise. 

Question: I presume that you mean pfd frequency, not oscin_p/n frequency?

Hello Noel,

OK, so in my example-1, the PLL noise is high, so the jitter on the output will be high.

Would you know how to translate the noise into a jitter value for example-1?

Let me ask a 2nd question: if I use two LMX2820 parts in series, then does the series combination reduce the jitter?

Below is an example where

-  the 1st pll has f_osc=640MHz

-  the 1st pll outputs 760MHz which goes to the osc input of the 2nd pll

-  the 2nd pll outputs f_out=2517.5MHz:

So the f_pfd of the 1st pll is 320MHz, & the f_pfd of the 2nd pll is 190MHz.

(note: in below example, N= iNput divider, M=Multiplier=feedback_divider, O=Output_divider)

EXAMPLE_3: f_out= 2517.5 MHz
1. PLL1
    REFCLK= 640.000000000000_MHz
    PFD_FREQ VCO_FREQ PLL_OUTPUT OUTPUT_ERROR N M O
    ------------ ------------ ------------ ------------ ------- ------- -------
    320.000000 6080.000000 760.000000 0.00000000% 2 19 8 
    160.000000 9120.000000 760.000000 0.00000000% 4 57 12 

2. PLL2
    REFCLK= 760.000000000000_MHz
    PFD_FREQ VCO_FREQ PLL_OUTPUT OUTPUT_ERROR N M O
    ------------ ------------ ------------ ------------ ------- ------- -------
    190.000000 10070.000000 2517.500000 0.00000000% 4 53 4

For a two PLL series combination, would you know whether two LMX2820 parts in series is preferred, or should I instead use a LMK04832 (or LMK04714) followed by a LMX2820? Some of TI's parts incorporate 2 PLLs internally in a single part.

Hello Noel,

In my example, I have two LMX2820 devices in series: the output of the 1st goes to the input of the 2nd. 

Both set C3=1.5nF.

The 1st has osc_input=640MHz, output=760MHz (output jitter=35.93_fs_rms from PLLatinum_Sim).

    N(input)_div=2, M(Multiplier=feedback)_div=19, O(Out_div)_div=8, f_pfd=320_MHz; f_out=760_MHz;

The 2nd has osc_input=760MHz, output=2517.5MHz (output jitter=36.73_fs_rms from PLLatinum_Sim).

    N(input)_div=4, M(Multiplier=feedback)_div=53, O(Out_div)_div=4, f_pfd=190_MHz; f_out=2517.5_MHz;

The question is: does the PLLatinum_Sim tool allow the user to set the jitter of the osc_input signal (in rms femto-seconds) in order to see the effect on the output jitter?

Who would know how to do that?

I also need to figure out how to set the output of the 1st pll to non-sine in order to crank up the slew rate (the parts on the board would be adjacent).

Also, I could not figure out how to insert a jpg of the PllatinumSim output into this message.

To answer your question: I was trying to get <100ppm of rms jitter (aka long term jitter).

The output of the 2nd PLL above shows:

    jitter_rms_ppm= 36.73e-15 / (1/2517.5e6) * 1e6= 92.467_ppm