LMK04828: LMK04828: sync pin sdclk(sysref) duty Cycle

I am using multiple LMK04828 and doing the same programming.

However, the DUTY CYCLE of each chip is output differently.
-1CHIP(LMK04828) : 50%,
-2CHIP(LMK04828): about ~56%(144mhz, 1CLOCK ERROR : 6.25%???) 
Is this correct?

Hello,

I think I am a bit confused about your SYNC pin usage. You mentioned that you are supplying a 9 MHz signal?

And I understand that there seems to be a duty cycle skew. Could you share your configuration file (either as a .tcs file or as a hex file) and your clock tree? I just need to get an idea of your inputs and your buffer configurations.

Thanks,

Michael

Yes, it supplies a plus 9MHz signal to the pin and outputs it as SDCLK ​​in divider mode.

Input 144MHz as CLKin and set it to FIN mode, then divide it down to DCLK in that mode and output it.

The peculiar thing is that the above programming satisfies 50% duty cycle on some chips, but does not occupy the chip on some.

lmk_wlr_set : vector_24bit (0~143) := -- 위치 13 산 비트 & 데이터 8 비트 
( 
x"000090", 
x"000010", 
x"000200", 
x"000306", 
x"0004D0", 
x"00055B", 
x"000600", 
x"000C51", 
x"000D04", 
x"010001", 
x"010111", 
x"010255", 
x"010302", 
x"010422",-- SDCLKout1_DDLY 채널 1 010422 
x"010500",--@@010500 
x"010600", 
x"010711", 
x"010801", 
x"010911", 
x"010A55", 
x"010B02", 
x"010C22", -- SDCLKout3_DDLY 채널 2 010C22 
x"010D00", -- 010D00 
x"010E00", 
x"010F11", 
x"011001", 
x"011111", 
x"011255", 
x"011302", 
x"011422", -- SDCLKout5_DDLY 채널 3 011422 
x"011500", -- 011500 
x"011600", 
x"011711", 
x"011801", 
x"011911", 
x"011A55", 
x"011B02", 
x"011C22", -- SDCLKout7_DDLY채널 4 011C22 
x"011D00", -- 011D00 
x"011E00", 
x"011F11", 
x"012001", 
x"012111", 
x"012255", 
x"012302", 
x"012422", -- SDCLKout9_DDLY채널 5 012422 
x"012500", --012500 
x"012600", 
x"012711", 
x"012801", 
x"012911", 
x"012A55", 
x"012B02", 
x"012C22", -- SDCLKout11_DDLY채널 6 012C22 
x"012D00", -- 012D00 
x"012E00", 
x"012F11", 
x"013001", 
x"013111", 
x"013255", 
x"013300", 
x"013402", 
x"013500", 
x"013629", 
x"013700", 
x"013840", 
x"013900", 
x"013A00", 
x"013B00", 
x"013C00", 
x"013D00", 
x"013E03", 
x"013F0E", 
x"0140F1", 
x"014100", 
x"014200", 
x"014391",-- @@ SYNCREF CLR 활성화 
x"014400",-- @@ SYNC DIS 모집 
x"01457F", 
x"014618",
x"014713", 
x"014804", -- 01480B 클로인 
x"014944", -- 01494B 클로인 
x"014A02", 
x"014B16", 
x"014C00", 
x"014D00", 
x"014EC0", 
x"014F7F", 
x"015003", 
x"015102", 
x"015200", 
x"015300", 
x"015478", 
x"015500", 
x"015678", 
x"015700", 
x"015896", 
x"015900", 
x"015A00", 
x"015BD4", 
x"015C20", 
x"015D00", 
x"015E00", 
x"015F0B", 
x"016000", 
x"016101", 
x"016244",
x"016300", 
x"016400", 
x"01650C", 
x"0171AA", 
x"017202", 
x"017C15", 
x"017D33", 
x"016600", 
x"016700", 
x"016809", 
x"016959", 
x"016A20", 
x"016B00", 
x"016C00", 
x"016D00", 
x"016E13", 
x"017320", 
x"018200", 
x"018300", 
x"018400", 
x"018500", 
x"018800", 
x"018900", 
x"018A00", 
x"018B00", 
x"1FFD00", 
x"1FFE00", 
x"1FFF53", 
x"013900", -- @@ SYSREF(SYNC PIN) 
x"014400", -- @@ SYNC DIS & SYNC_DISx 
x"0143B1", -- @@ SYNCPOL 활성화 
x"014391", -- @@ SYNCPOL 소개 ,,, 
x"014480", -- @@ SYNC DIS 활성화 
x"0144FF", -- @@ SYNC DIS 활성화 & SYNC_DISx 활성화 
x"014311", -- @@ SYNCREF CLR 
x"1FFF53" -- 데이터 데이터 
);

And SDCLK ​​​​output is output only when SDCLK ​​​​​​DIGITAL DELAY value is set to 2CYCLES. (SDCLK ​​​​​​output is output when BYPASS.)

Hello again,

Thank you for sharing all of that. It is a bit difficult for me to be able to input that into TICS Pro easily. Can you go into TICS Pro, click File, and then click Save in the dropdown menu. This will save a .tcs file that will allow me to emulate your setup with the greatest fidelity.

However, there are a couple things that I would like you to change. As I understand it, you use distribution mode in order to route the reference signal to CLKin1 to your outputs. Could you set the SYSREF Divider value to 1 instead of 0? Additionally, instead of using a 9 MHz signal as the input to the SYNC pin, could you just use the SYNC_POL bit? The 9 MHz signal is not going to continuously re-sync the device upon each rising edge of the signal, which may cause some issues.

Thanks,

Michael

x"013900", -- @@ SYSREF(SYNC PIN) 
x"014400", -- @@ SYNC DIS & SYNC_DISx 
x"0143B1", -- @@ SYNCPOL 활성화 
x"014391", -- @@ SYNCPOL 소개 ,,, 
x"014480", -- @@ SYNC DIS 활성화 
x"0144FF", -- @@ SYNC DIS 활성화 & SYNC_DISx 활성화 
x"014311", -- @@ SYNCREF CLR 
x"1FFF53" -- 데이터 데이터 

The above part is the part added to reset the .tcs file.
TICSPRO_exam.tcs

The 9MHz signal is a signal generated and input from outside the system, so the structure does not allow the use of the SYNC_POL bit.

Do I need to resync the 9MHz signal every clock cycle?

Can't we use it by initializing it with the SYNC_POL bit as below?

I'm in distribution mode, do I need to resync?

x"013900", -- @@ SYSREF(SYNC PIN) 
x"014400", -- @@ SYNC DIS & SYNC_DISx 
x"0143B1", -- @@ SYNCPOL 활성화 
x"014391", -- @@ SYNCPOL 소개 ,,, 
x"014480", -- @@ SYNC DIS 활성화 
x"0144FF", -- @@ SYNC DIS 활성화 & SYNC_DISx 활성화 
x"014311", -- @@ SYNCREF CLR 
x"1FFF53" -- 데이터 데이터

My purpose is to use multiple lmk04828s to use DCLK distribution mode and SDCLK ​​distribution mode.

When used like this,

the output DUTY CYCLE of SDCLK ​​for each lmk04828 is different as follows.

dclk: Is it possible for a duty cycle error to occur as much as 1 clock of 144mhz?

-1CHIP(LMK04828): 50%, 
-2CHIP(LMK04828): about ~56%(144mhz, 1CLOCK ERROR: 6.25%???) 

I'm also curious about the following problem.
- SDCLK ​​​​output is output only when SDCLK ​​​​​​DIGITAL DELAY value is set to 2CYCLES. (SDCLK ​​​​​​output is not output when BYPASS.)

Hello,

I understand the issue you are having with the duty cycle discrepancy between outputs. I will take your configuration into lab in order to determine if I can replicate the issue. Can you specify which outputs (designating which board, as well) are outputting 50% dc, and which are outputting 56% dc?

Additionally, I am a bit confused about what you are trying to do with the 9 MHz signal. I understand that it is generated and input from outside the system, but why are you inputting it to the SYNC pin? It cannot synchronize the signals being output by the LMK04828 as effectively as a single rising edge to the SYNC pin or the SYNC_POL bit can. Additionally, it seems like you want the 9 MHz signal to be synchronized? Which can only be done if it is input to a clock input. 

Thanks,

Michael

I am using multiple LMK04828s on one board. 

Some LMK04828s output a duty cycle of (SDCLK)50%, while others output a duty cycle of

(SDCLK)56%. I tested multiple boards to see if it is a board-specific issue, and the duty cycles are all different for each board

so I suspect it is a LMK04828 chip-specific issue.

What is unique is that the SDCLK ​​duty cycle is different by 1 clock time of dclk 144mhz.

144mhz, 9mhz should be output as 16 channels each. Since many LMK04828s are used, I want to configure 144mhz:dclk, 9mhz:sdclk distribution mode to use the minimum number of LMK04828s.

144mhz, 9mhz are trying to match using sdclk digital delay if they are out of sync. 
144mhz, 9mhz do not need to be exactly in sync.

 
I'm also curious about the following problem.
- SDCLK ​​​​output is output only when SDCLK ​​​​​​DIGITAL DELAY value is set to 2CYCLES. (SDCLK ​​​​​​output is not output when BYPASS.

Personally, I think there is no problem in programming since there is LMK04828s that satisfy the duty cycle of (SDCLK)50%.

However, although it should generally satisfy the duty cycle of 50%, can there be an error of 1 clock of the dclk frequency((SDCLK)56%)?

Hello,

When you say that the SDCLK duty cycle is different by 1 clock time of the DCLK, do you mean that it differs by the length of one period of the DCLK (6.944 ns)? 

Additionally, instead of setting your SYSREF_MUX to Normal SYNC mode, could you try setting it to SYSREF Continuous mode? SYSREF Continuous mode is what will result in the desired SYSREF outputs. They will be output as soon as the first SYNC event occurs. 

Finally, could you provide a scope shot showing the differing duty cycles? 

Thanks,

Michael

Yes, that's right. It's different by one cycle of DCLK (6.944ns).

sysref continuous mode is fine. However, it becomes a problem when using external sync.

I need to distribute and use externally input synchronous signals.
I can't use internal sysrefs.

DUTY CYCLE does not appear in various forms between 50% and 56%, It only outputs 50% or 56%.

Hello again,

Looking over your configuration, I am a bit confused as to why you set the SYSREF divider value to 0. I would expect that to result in some unanticipated behavior. Would it be possible for you to set that to 1, and then instead of inputting a 9 MHz signal to the SYNC pin, could you just input a single rising edge? The SYNC pin phase aligns the output dividers and is required to output a SYSREF signal - you bypass the output dividers so that should not be an issue, but you need a SYNC event to generate your SYSREF outputs. The fact that you have a 9 MHz signal going to the SYNC pin means that your SYSREF outputs will be muted and re-aligned 9 million times per second - I have a feeling that is the source of the duty cycle distortion. 

Thanks,

Michael

Okay, I see. Let's set the sysref divider value to 1 and input a single rising edge with snc_pol as shown below.

The fact that you have a 9 MHz signal going to the SYNC pin means that your SYSREF outputs will be muted and re-aligned 9 million times per second - I have a feeling that this is the source of the duty cycle distortion.

=> If the above is the cause, how about inputting ClKin0 instead of sync pin?

I'm also curious about the following problem.
- SDCLK ​​​​​​output is output only when SDCLK ​​​​​​​​DIGITAL DELAY value is set to 2CYCLES. (SDCLK ​​​​​​​​output is not output when BYPASS.)

The fact that you have a 9 MHz signal going to the SYNC pin means that your SYSREF outputs will be muted and re-aligned 9 million times per second - I have a feeling that this is the source of the duty cycle distortion.

=> Among the many lmk04828s I am using, some output 50% duty cycle. 

How should I interpret this?

Hello again,

park joon man said:

=> If the above is the cause, how about inputting ClKin0 instead of sync pin?

The CLKin0 and SYNC pin work identically for SYNC functionality. A SYNC event requires a single rising edge or a single toggle of the SYNC_POL bit. Inputting a CLK signal to the input pin configured for a SYNC signal will result in inappropriate behavior. 

park joon man said:

=> Among the many lmk04828s I am using, some output 50% duty cycle. How should I interpret this?

You mentioned that the 56% duty cycle only appears on the SDCLK outputs. This could be explained by the way the SYNC pin is being treated. You bypass the output dividers for all of the DCLK outputs - meaning the DCLK outputs are unimpacted by any SYNC event, since the output dividers being re-aligned has no bearing on the outputs. However, the SDCLK outputs will be impacted, since a SYNC event is required to generate SYSREF outputs. But now you have confused me a little. Are your SYSREF outputs 144 MHz or 9 MHz?

Thanks,

Michael

SYSREF output: 9mhz

DLCK output: 144mhz

Doesn't the degital logic of SYSREF use the clock of vco(clkin1,external VCO,144mhz)?
So I thought that sdclk duty 56% is related to 1clock time of 144mhz
*******
dclk output <= VCO(144mhz)

Isn't setting the sysref divider value to 1 used when an internal SYSREF occurs? I'm using external SYNC

Thank you.

I'm also curious about the following problem.
- SDCLK ​​​​​​output is output only when SDCLK ​​​​​​​​DIGITAL DELAY value is set to 2CYCLES. (SDCLK ​​​​​​​​output is not output when BYPASS.

And when you say that you can't re-clock, does that mean that SDCLK ​​​​​​​​DIGITAL DELAY doesn't work?

Hello,

I will be able to answer on Monday.

Thanks,

Michael

I'm also curious about the following problem.
- SDCLK ​​​​​​output is output only when SDCLK ​​​​​​​​DIGITAL DELAY value is set to 2CYCLES. (SDCLK ​​​​​​​​output is not output when BYPASS.

And when you say that you can't re-clock, does that mean that SDCLK ​​​​​​​​DIGITAL DELAY doesn't work?

Hello,

park joon man said:

SDCLK ​​​​​​output is output only when SDCLK ​​​​​​​​DIGITAL DELAY value is set to 2CYCLES. (SDCLK ​​​​​​​​output is not output when BYPASS.

Your SDCLK output only appears when the digital delay circuitry is not bypassed. Does it still appear when the number of cycles is increased? Does it appear for 3, 4, or 5 cycles? Does it still occur with the update configuration?

park joon man said:

And when you say that you can't re-clock, does that mean that SDCLK ​​​​​​​​DIGITAL DELAY doesn't work?

No, what I mean by this is that you cannot use the SYNC pin to re-clock your signal to the SYSREF path. The circuitry of the SYNC pin is not such that a clock signal may be fed into it, you should be using CLKin0 to do this.

Thanks,

Michael

the output DUTY CYCLE of SDCLK ​​for each lmk04828 is different as follows.
-1CHIP(LMK04828): 50%,
-2CHIP(LMK04828): about ~56%(144mhz, 1CLOCK ERROR: 6.25%???)

-1CHIP(LMK04828): 50%

How should I interpret the above 50% occurrence?

Hello,

If this issue has persisted through the various configuration files, then it seems that there may be an issue with your output driver. I will speak to a designer to confirm the source of your issues. In the meantime, could you provide a full schematic?

Thanks,

Michael

Hi again,

Can you share the clock source with me?

Thanks,

Michael

The clock source is input externally.

Hello,

Would you be able to measure the input on an oscilloscope?

Thanks,

Michael

I am inputting a 9MHz square wave . I can see the output because it is input correctly

Hi again,

I am confused. I thought you were inputting a 144 MHz signal to CLKin1. Can you show me an oscilloscope measurement? Why are you inputting a 9 MHz signal to CLKin1 - you are using buffer mode, which will output whatever signal frequency that you input.

Thanks,

Michael

SYNC Pin : 9MHz, CLKin : 144MHz

I told you that SDCLK ​​9mhz is causing an error

the output DUTY CYCLE of SDCLK ​​for each lmk04828 is different as follows.
-1CHIP(LMK04828): 50%,
-2CHIP(LMK04828): about ~56%(144mhz, 1CLOCK ERROR: 6.25%???)

-1CHIP(LMK04828): 50%

How should I interpret the above 50% occurrence?

As I have stated earlier, you cannot input a clock signal to the SYNC pin. The SYNC pin is only configured to receive a rising edge. 

Based on what I have seen so far, I believe the duty cycle distortion is either the result of improper use of the SYNC pin, or there is an issue with the input signal. Please try inputting the 9 MHz signal to CLKin0, using the configuration I attached above, and measuring the input signal and sending me a screenshot. I am curious to see what it looks like.

Thanks,

Michael

As I have stated earlier, you cannot input a clock signal to the SYNC pin. The SYNC pin is only configured to receive a rising edge. 

=> Why does it start with 50% duty output? 
If you can't input a clock signal, shouldn't there be no output?

Hi again,

Above the highlighted portion, Derek mentions the SYNC_DISSYSREF bit. Do you have that bit cleared?

Furthermore, given that you bypass the clock output dividers, I am skeptical that your duty cycle distortion is the result of an odd divide value. 

Could you try setting the Clock Output Select as with the setting I have highlighted? This will enable duty cycle correction, which would solve the issue if it were as Derek writes.

Thanks,

Michael

Are you telling me to set this up?

Yes please.

Thanks,

Michael

Are you saying to do the above with the input set to 9MHz SYNC, not 9MHz clkin0?

For now, do it with your input set as it is - with the 9 MHz signal going to the SYNC pin. 

Thank you
I can't check right now because I don't have the board, but I can do it in 2 weeks.

1. It is recommended to use a pulse-type signal for the SYNC pin

2. It is recommended to use CLKin0, which is a continuous pulse type signal

Can I organize it like this?

Hi again,

1. is correct. 2. is also correct, but it is important to add that CLKin0 can be used as the SYNC source, or it may be used to re-clock a signal along the SYSREF path, which is what I believe you are trying to do with the 9 MHz signal. 

Furthermore, for the sake of debugging, the Clock Output Select should be set to Divider+DCC+HS, as that should provide duty cycle correction - but only if the clock divider is used.

Thanks,

Michael

I'm curious. The current duty of sdclk(Sysref) is in a strange state.

Isn't the setting below related to the duty setting of dclk, not sdclk(sysref)?

You are right, this is related to the settings of DCLK, not SDCLK, my mistake. Please try the previous recommendations when the board comes back, as I believe the issue is related to the way the SYNC pin is interfaced. 

Thanks,

Michael