LMK04828: LMK04828: sync pin sdclk(sysref) duty Cycle

park joon man

Part Number: LMK04828

Tool/software:

LMK04828: 
DCLK :144MHz 
SYNC PIN :9MHz Under the condition, sdclk(sysref) duty cycle is not 50%. 
In the sdclk(sysref) output port Some output ports satisfy 50%, but othersdclk(sysref) output ports are around 56%.

I'm curious about the cause

11 days ago

0 park joon man 11 days ago

Prodigy 10 points

I am using multiple LMK04828 and doing the same programming.

However, the DUTY CYCLE of each chip is output differently.
-1CHIP(LMK04828) : 50%,
-2CHIP(LMK04828): about ~56%(144mhz, 1CLOCK ERROR : 6.25%???) 
Is this correct?

0 Michael Srinivasan 10 days ago in reply to park joon man

TI__Expert 4940 points

Hello,

I think I am a bit confused about your SYNC pin usage. You mentioned that you are supplying a 9 MHz signal?

And I understand that there seems to be a duty cycle skew. Could you share your configuration file (either as a .tcs file or as a hex file) and your clock tree? I just need to get an idea of your inputs and your buffer configurations.

Thanks,

Michael

0 park joon man 10 days ago in reply to Michael Srinivasan

Prodigy 10 points

Yes, it supplies a plus 9MHz signal to the pin and outputs it as SDCLK in divider mode.

Input 144MHz as CLKin and set it to FIN mode, then divide it down to DCLK in that mode and output it.

The peculiar thing is that the above programming satisfies 50% duty cycle on some chips, but does not occupy the chip on some.


lmk_wlr_set : vector_24bit (0~143) := -- 위치 13 산 비트 & 데이터 8 비트 
( 
x"000090", 
x"000010", 
x"000200", 
x"000306", 
x"0004D0", 
x"00055B", 
x"000600", 
x"000C51", 
x"000D04", 
x"010001", 
x"010111", 
x"010255", 
x"010302", 
x"010422",-- SDCLKout1_DDLY 채널 1 010422 
x"010500",--@@010500 
x"010600", 
x"010711", 
x"010801", 
x"010911", 
x"010A55", 
x"010B02", 
x"010C22", -- SDCLKout3_DDLY 채널 2 010C22 
x"010D00", -- 010D00 
x"010E00", 
x"010F11", 
x"011001", 
x"011111", 
x"011255", 
x"011302", 
x"011422", -- SDCLKout5_DDLY 채널 3 011422 
x"011500", -- 011500 
x"011600", 
x"011711", 
x"011801", 
x"011911", 
x"011A55", 
x"011B02", 
x"011C22", -- SDCLKout7_DDLY채널 4 011C22 
x"011D00", -- 011D00 
x"011E00", 
x"011F11", 
x"012001", 
x"012111", 
x"012255", 
x"012302", 
x"012422", -- SDCLKout9_DDLY채널 5 012422 
x"012500", --012500 
x"012600", 
x"012711", 
x"012801", 
x"012911", 
x"012A55", 
x"012B02", 
x"012C22", -- SDCLKout11_DDLY채널 6 012C22 
x"012D00", -- 012D00 
x"012E00", 
x"012F11", 
x"013001", 
x"013111", 
x"013255", 
x"013300", 
x"013402", 
x"013500", 
x"013629", 
x"013700", 
x"013840", 
x"013900", 
x"013A00", 
x"013B00", 
x"013C00", 
x"013D00", 
x"013E03", 
x"013F0E", 
x"0140F1", 
x"014100", 
x"014200", 
x"014391",-- @@ SYNCREF CLR 활성화 
x"014400",-- @@ SYNC DIS 모집 
x"01457F", 
x"014618",
x"014713", 
x"014804", -- 01480B 클로인 
x"014944", -- 01494B 클로인 
x"014A02", 
x"014B16", 
x"014C00", 
x"014D00", 
x"014EC0", 
x"014F7F", 
x"015003", 
x"015102", 
x"015200", 
x"015300", 
x"015478", 
x"015500", 
x"015678", 
x"015700", 
x"015896", 
x"015900", 
x"015A00", 
x"015BD4", 
x"015C20", 
x"015D00", 
x"015E00", 
x"015F0B", 
x"016000", 
x"016101", 
x"016244",
x"016300", 
x"016400", 
x"01650C", 
x"0171AA", 
x"017202", 
x"017C15", 
x"017D33", 
x"016600", 
x"016700", 
x"016809", 
x"016959", 
x"016A20", 
x"016B00", 
x"016C00", 
x"016D00", 
x"016E13", 
x"017320", 
x"018200", 
x"018300", 
x"018400", 
x"018500", 
x"018800", 
x"018900", 
x"018A00", 
x"018B00", 
x"1FFD00", 
x"1FFE00", 
x"1FFF53", 
x"013900", -- @@ SYSREF(SYNC PIN) 
x"014400", -- @@ SYNC DIS & SYNC_DISx 
x"0143B1", -- @@ SYNCPOL 활성화 
x"014391", -- @@ SYNCPOL 소개 ,,, 
x"014480", -- @@ SYNC DIS 활성화 
x"0144FF", -- @@ SYNC DIS 활성화 & SYNC_DISx 활성화 
x"014311", -- @@ SYNCREF CLR 
x"1FFF53" -- 데이터 데이터 
);

And SDCLK output is output only when SDCLK DIGITAL DELAY value is set to 2CYCLES. (SDCLK output is output when BYPASS.)

0 Michael Srinivasan 10 days ago in reply to park joon man

TI__Expert 4940 points

Hello again,

Thank you for sharing all of that. It is a bit difficult for me to be able to input that into TICS Pro easily. Can you go into TICS Pro, click File, and then click Save in the dropdown menu. This will save a .tcs file that will allow me to emulate your setup with the greatest fidelity.

However, there are a couple things that I would like you to change. As I understand it, you use distribution mode in order to route the reference signal to CLKin1 to your outputs. Could you set the SYSREF Divider value to 1 instead of 0? Additionally, instead of using a 9 MHz signal as the input to the SYNC pin, could you just use the SYNC_POL bit? The 9 MHz signal is not going to continuously re-sync the device upon each rising edge of the signal, which may cause some issues.

Thanks,

Michael

0 park joon man 10 days ago in reply to Michael Srinivasan

Prodigy 10 points

x"013900", -- @@ SYSREF(SYNC PIN) 
x"014400", -- @@ SYNC DIS & SYNC_DISx 
x"0143B1", -- @@ SYNCPOL 활성화 
x"014391", -- @@ SYNCPOL 소개 ,,, 
x"014480", -- @@ SYNC DIS 활성화 
x"0144FF", -- @@ SYNC DIS 활성화 & SYNC_DISx 활성화 
x"014311", -- @@ SYNCREF CLR 
x"1FFF53" -- 데이터 데이터

The above part is the part added to reset the .tcs file.
TICSPRO_exam.tcs

The 9MHz signal is a signal generated and input from outside the system, so the structure does not allow the use of the SYNC_POL bit.

Do I need to resync the 9MHz signal every clock cycle?

Can't we use it by initializing it with the SYNC_POL bit as below?

I'm in distribution mode, do I need to resync?

x"013900", -- @@ SYSREF(SYNC PIN) 
x"014400", -- @@ SYNC DIS & SYNC_DISx 
x"0143B1", -- @@ SYNCPOL 활성화 
x"014391", -- @@ SYNCPOL 소개 ,,, 
x"014480", -- @@ SYNC DIS 활성화 
x"0144FF", -- @@ SYNC DIS 활성화 & SYNC_DISx 활성화 
x"014311", -- @@ SYNCREF CLR 
x"1FFF53" -- 데이터 데이터

0 park joon man 10 days ago in reply to park joon man

Prodigy 10 points

My purpose is to use multiple lmk04828s to use DCLK distribution mode and SDCLK distribution mode.

When used like this,

the output DUTY CYCLE of SDCLK for each lmk04828 is different as follows.

dclk: Is it possible for a duty cycle error to occur as much as 1 clock of 144mhz?

-1CHIP(LMK04828): 50%, 
-2CHIP(LMK04828): about ~56%(144mhz, 1CLOCK ERROR: 6.25%???) 

I'm also curious about the following problem.
- SDCLK output is output only when SDCLK DIGITAL DELAY value is set to 2CYCLES. (SDCLK output is not output when BYPASS.)

0 Michael Srinivasan 9 days ago in reply to park joon man

TI__Expert 4940 points

Hello,

I understand the issue you are having with the duty cycle discrepancy between outputs. I will take your configuration into lab in order to determine if I can replicate the issue. Can you specify which outputs (designating which board, as well) are outputting 50% dc, and which are outputting 56% dc?

Additionally, I am a bit confused about what you are trying to do with the 9 MHz signal. I understand that it is generated and input from outside the system, but why are you inputting it to the SYNC pin? It cannot synchronize the signals being output by the LMK04828 as effectively as a single rising edge to the SYNC pin or the SYNC_POL bit can. Additionally, it seems like you want the 9 MHz signal to be synchronized? Which can only be done if it is input to a clock input.

Thanks,

Michael

0 park joon man 9 days ago in reply to Michael Srinivasan

Prodigy 10 points

I am using multiple LMK04828s on one board. 

Some LMK04828s output a duty cycle of (SDCLK)50%, while others output a duty cycle of

(SDCLK)56%. I tested multiple boards to see if it is a board-specific issue, and the duty cycles are all different for each board

so I suspect it is a LMK04828 chip-specific issue.

What is unique is that the SDCLK duty cycle is different by 1 clock time of dclk 144mhz.

144mhz, 9mhz should be output as 16 channels each. Since many LMK04828s are used, I want to configure 144mhz:dclk, 9mhz:sdclk distribution mode to use the minimum number of LMK04828s.

144mhz, 9mhz are trying to match using sdclk digital delay if they are out of sync. 
144mhz, 9mhz do not need to be exactly in sync.

 
I'm also curious about the following problem.
- SDCLK output is output only when SDCLK DIGITAL DELAY value is set to 2CYCLES. (SDCLK output is not output when BYPASS.

0 park joon man 9 days ago in reply to park joon man

Prodigy 10 points

Personally, I think there is no problem in programming since there is LMK04828s that satisfy the duty cycle of (SDCLK)50%.

However, although it should generally satisfy the duty cycle of 50%, can there be an error of 1 clock of the dclk frequency((SDCLK)56%)?

0 Michael Srinivasan 8 days ago in reply to park joon man

TI__Expert 4940 points

Hello,

When you say that the SDCLK duty cycle is different by 1 clock time of the DCLK, do you mean that it differs by the length of one period of the DCLK (6.944 ns)?

Additionally, instead of setting your SYSREF_MUX to Normal SYNC mode, could you try setting it to SYSREF Continuous mode? SYSREF Continuous mode is what will result in the desired SYSREF outputs. They will be output as soon as the first SYNC event occurs.

Finally, could you provide a scope shot showing the differing duty cycles?

Thanks,

Michael

0 park joon man 8 days ago in reply to Michael Srinivasan

Prodigy 10 points

Yes, that's right. It's different by one cycle of DCLK (6.944ns).

sysref continuous mode is fine. However, it becomes a problem when using external sync.

I need to distribute and use externally input synchronous signals.
I can't use internal sysrefs.

DUTY CYCLE does not appear in various forms between 50% and 56%, It only outputs 50% or 56%.

0 Michael Srinivasan 7 days ago in reply to park joon man

TI__Expert 4940 points

Hello again,

Looking over your configuration, I am a bit confused as to why you set the SYSREF divider value to 0. I would expect that to result in some unanticipated behavior. Would it be possible for you to set that to 1, and then instead of inputting a 9 MHz signal to the SYNC pin, could you just input a single rising edge? The SYNC pin phase aligns the output dividers and is required to output a SYSREF signal - you bypass the output dividers so that should not be an issue, but you need a SYNC event to generate your SYSREF outputs. The fact that you have a 9 MHz signal going to the SYNC pin means that your SYSREF outputs will be muted and re-aligned 9 million times per second - I have a feeling that is the source of the duty cycle distortion.

Thanks,

Michael

0 park joon man 7 days ago in reply to Michael Srinivasan

Prodigy 10 points

Okay, I see. Let's set the sysref divider value to 1 and input a single rising edge with snc_pol as shown below.

The fact that you have a 9 MHz signal going to the SYNC pin means that your SYSREF outputs will be muted and re-aligned 9 million times per second - I have a feeling that this is the source of the duty cycle distortion.

=> If the above is the cause, how about inputting ClKin0 instead of sync pin?

I'm also curious about the following problem.
- SDCLK output is output only when SDCLK DIGITAL DELAY value is set to 2CYCLES. (SDCLK output is not output when BYPASS.)

0 park joon man 7 days ago in reply to park joon man

Prodigy 10 points

=> Among the many lmk04828s I am using, some output 50% duty cycle. 

How should I interpret this?

0 Michael Srinivasan 7 days ago in reply to park joon man

TI__Expert 4940 points

Hello again,

park joon man said:
=> If the above is the cause, how about inputting ClKin0 instead of sync pin?

The CLKin0 and SYNC pin work identically for SYNC functionality. A SYNC event requires a single rising edge or a single toggle of the SYNC_POL bit. Inputting a CLK signal to the input pin configured for a SYNC signal will result in inappropriate behavior.

park joon man said:
=> Among the many lmk04828s I am using, some output 50% duty cycle. How should I interpret this?

You mentioned that the 56% duty cycle only appears on the SDCLK outputs. This could be explained by the way the SYNC pin is being treated. You bypass the output dividers for all of the DCLK outputs - meaning the DCLK outputs are unimpacted by any SYNC event, since the output dividers being re-aligned has no bearing on the outputs. However, the SDCLK outputs will be impacted, since a SYNC event is required to generate SYSREF outputs. But now you have confused me a little. Are your SYSREF outputs 144 MHz or 9 MHz?

Thanks,

Michael

0 park joon man 7 days ago in reply to Michael Srinivasan

Prodigy 10 points

SYSREF output: 9mhz

DLCK output: 144mhz

0 park joon man 7 days ago in reply to park joon man

Prodigy 10 points

Doesn't the degital logic of SYSREF use the clock of vco(clkin1,external VCO,144mhz)?
So I thought that sdclk duty 56% is related to 1clock time of 144mhz
*******
dclk output <= VCO(144mhz)

0 park joon man 7 days ago in reply to park joon man

Prodigy 10 points

Isn't setting the sysref divider value to 1 used when an internal SYSREF occurs? I'm using external SYNC

0 Michael Srinivasan 6 days ago in reply to park joon man

TI__Expert 4940 points

Hi again,

I think I have a better understanding of your system now. You input 144 MHz into CLKin1 and use distribution mode to send that to the output dividers - which you bypass.

You cannot re-clock your 9 MHz input to the SYNC pin along the SYSREF distribution path. However, you can re-clock your SYSREF signal through CLKin0. I have attached a configuration that I used to get this to work. I input 144 MHz to CLKin1, which was sent to the DCLK outputs. I also input 9 MHz to CLKin0, which I routed to the SYSREF_MUX. I chose re-clocked as the SYSREF output mode, and chose CLKin0 as the signal to send along the SYSREF distribution path. I was able to see a 9 MHz output with a 50% duty cycle at the SDCLK outputs.

correct_clktree_config.tcs

Thanks,

Michael

0 park joon man 6 days ago in reply to Michael Srinivasan

Prodigy 10 points

Thank you.

I'm also curious about the following problem.
- SDCLK output is output only when SDCLK DIGITAL DELAY value is set to 2CYCLES. (SDCLK output is not output when BYPASS.

And when you say that you can't re-clock, does that mean that SDCLK DIGITAL DELAY doesn't work?

0 Michael Srinivasan 6 days ago in reply to park joon man

TI__Expert 4940 points

Hello,

I will be able to answer on Monday.

Thanks,

Michael

0 park joon man 2 days ago in reply to Michael Srinivasan

Prodigy 10 points

I'm also curious about the following problem.
- SDCLK output is output only when SDCLK DIGITAL DELAY value is set to 2CYCLES. (SDCLK output is not output when BYPASS.

And when you say that you can't re-clock, does that mean that SDCLK DIGITAL DELAY doesn't work?

0 Michael Srinivasan 1 day ago in reply to park joon man

TI__Expert 4940 points

Hello,

park joon man said:
SDCLK output is output only when SDCLK DIGITAL DELAY value is set to 2CYCLES. (SDCLK output is not output when BYPASS.

Your SDCLK output only appears when the digital delay circuitry is not bypassed. Does it still appear when the number of cycles is increased? Does it appear for 3, 4, or 5 cycles? Does it still occur with the update configuration?

park joon man said:
And when you say that you can't re-clock, does that mean that SDCLK DIGITAL DELAY doesn't work?

No, what I mean by this is that you cannot use the SYNC pin to re-clock your signal to the SYSREF path. The circuitry of the SYNC pin is not such that a clock signal may be fed into it, you should be using CLKin0 to do this.

Thanks,

Michael

0 park joon man 2 hours ago in reply to Michael Srinivasan

Prodigy 10 points

the output DUTY CYCLE of SDCLK for each lmk04828 is different as follows.
-1CHIP(LMK04828): 50%,
-2CHIP(LMK04828): about ~56%(144mhz, 1CLOCK ERROR: 6.25%???)

-1CHIP(LMK04828): 50%

How should I interpret the above 50% occurrence?

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LMK04828: LMK04828: sync pin sdclk(sysref) duty Cycle