LMK04828: LMK04828 Sync and SYSREF

Hello Shekhar,

The SYSREF divider divides the VCO frequency to create a SYSREF output frequency that acts as a common timing reference for multiple devices in a JESD204B system.

A further description of the SYNC/SYSREF feature of the LMK04828 can be found in section 9.3.1 and 9.3.2 of the LMK04828 data sheet. The following link as provides more insight into the SYNC/SYSREF functionalities: Understanding JESD204B Subclasses and Deterministic Latency

The LMK04828 SYSREF divider clocks a D flip-flop that accepts an input from CLKin0 or the SYNC pin with the proper mux settings. The output of this D flip-flop can be selected through the re-clocked mode of the SYSREF_MUX to drive the SYNC/SYSREF distribution path. When the reference input to the LMK is the same frequency as the output of the SYSREF divider which clocks D flip-flop, and the PLL is using a ZDM feedback clock at the same frequency as the output of the SYSREF divider, then a CLKin0 or SYNC signal meeting setup and hold times to the reference input can be used to perform (1) a deterministic divider reset and/or (2) re-clock SYSREF clock onto the SYSREF outputs of the LMK.

Section 5 in the following document will provide a further description on the re-clocking SYNC:  Synchronization of Multiple LMK0482x Devices

Regards,

Kia Rahbar