Tool/software:
Hello,
I have a design using LMKDB1108 as a buffer and clock monitor. The clock is suppled to the design from an external piece of equipment. There is an on-bord microcontroller that is responsible for configuring and controlling buffer (among other things).
From the datasheet:
8.3.2.3 PWRGD Assertion
The first low-to-high transition of the PWRGD pin after device power is on can occur while input clock is running,
floating, low/low or pulled to VDD. The power-up sequence only starts if the PWRGD pin is pulled from low to
high while input clock is valid.
If the PWRGD pin is pulled from low to high while input clock is invalid, then the power-up sequence is not
initiated and the outputs stay low/low.
My issues are:
- prior to the power-up sequence completing, the chip responds to i2c communications and LOS# reports a valid clock.
- due to cable being unplugged, damaged, or clock not running. I have no idea if the power-up sequence completed.
- I don't see any status bits in the LMKDB1108 that are documented to mean the power-up sequence completed successfully.
- the design dose not have any other clock monitoring function, we are counting on the LMKDB1108 to provide this function.
As a consequence the microcontroller can not distinguish between conditions where the LMKDB1108 started with a good clock and LMKDB1108 failed to complete power-up sequence.
Am i missing something?
Thank you
Link
