Jitter Requirements for PCIe

Hi Adam,

here a list of currently available device which meets the PCIE gen2/gen3 requirements.

CDCM9102: low noise, 2ch 100MHz clock generator;

CDCM6100x: Low Jitter clock generator, pin mode are available for this device to generate other frequencies requested by the system;

CDCM6208: Flexible and Low Power clock genetor which can work in jitter cleaner mode as well.

We would be glad to offer further support where needed.

Best regards,

Leandro

Could you provide insight into what jitter performance is needed from a specification standpoint?

Thank you,

Adam

Hi Adam and everybody who is dealing with PCIE clocks,

please find attached a pdf about clock requirements for different PCIE generations. About rms for the PCIE gen3, the requested performance are referred after the system instrinc jitter filtering. For more details I will attached on the next thread a slide set from PCI SIG, which contains more detail on the jitter transfer function.

Best regards,

Leandro

For some PCIe applications that require HCSL clock signal format, I recommend the following TI clock fanout/distribution device which have low additive jitter, pin-configurable output signal format, and selectable universal inputs:

• LMK00301 - 3:10 fanout, HCSL/LVPECL/LVDS outputs, universal inputs (differential, single-ended, or crystal)
• LMK00308 - 3:8 fanout, HCSL/LVPECL/LVDS outputs, universal inputs (differential, single-ended, or crystal)
• LMK00306 - 3:6 fanout, HCSL/LVPECL/LVDS outputs, universal inputs (differential, single-ended, or crystal)
• LMK00304 - 3:4 fanout, HCSL/LVPECL/LVDS outputs, universal inputs (differential, single-ended, or crystal)
• CDCUN1208LP - 2:8 fanout, HCSL/LVDS/LVCMOS outputs, differential/single-ended inputs, input divider option

Regards,
Alan