This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

32MHz out of 10MHz reference

Other Parts Discussed in Thread: CLOCKDESIGNTOOL, LMK03033, LMK03002, LMK03806, ADS6442, LMK00105, CDCE925, CDCLVC1310


I am looking for optimal solution (IC) to generate 32MHz clock from 10MHz reference.

The needed 32MHz frequency if fixed.

(As next step I need to split the 32MHz into 4 outputs but this can be handled byanother IC.)

I am looking for compact and easy to handle solution.

I appreciate competent advice.

Thank you,



  • Hello Andre,

    We have numerous parts which can do this for you.  I might suggest you download the clock design tool (, which can help you pick the LMK part and design the loop filter for the you need.

      - There is some extra info needed.  (1) what is the input clock format required at the next IC?  LVCMOS/LVDS/LVPECL?  (2) are there any specific jitter/phase noise requirements needed?  If rms jitter is specified, integration bandwidth must also be specified.  12 kHz to 20 MHz for instance is a common integration bandwidth.  If peak to peak jitter is specified, a bit error rate should also be specified.

      - You may consider LMK03002 (48 pin 7x7 mm).  It can accept 10 MHz in and produce 4x 32 MHz LVPECL outputs.  LMK03033 has both 4x LVDS and 4x LVPECL outputs available.

      - You may consider LMK03806 (64 pin 9x9 mm).  It can accept 10 MHz in and product 12x 32 Mhz outputs, the output formats are programmable (LVDS/LVPECL/LVCMOS).

    One note, the slew rate of your 10 MHz clock should be > 0.15 V/ns.  What is the input format of this clock?

    My colleagues may be able to recommend some CDC parts for the same application.



  • Hello Timothy,

    Thank you for your reply. I will certainly check the parts you recommended.

    To answer your questions, required Clock Format is LVCMOS.

    Jitter of 10 MHz clock 1ps rms in bandwidth 12 kHz to 20 MHz. We would like to keep the ultra low jitter since it is used for ADC and DAC (TI parts ADS6442 and AD9117).

    Slew rate I do not know but on the Scope it looks pretty rectangular

  • Hello Timothy,

    As of now, my collegues adviced me to use Analog Devices synthesizer which they think will be easier to manage.

    I still plan to use buffer fanout ic from your catalog. The part thay would be really suitable would be LMK00105. However it has a package impossible to solder by hand. Hence prototyping will create issues. Is there a part with similar architecture but in differnt pckage? 


  • Hello Andrey,

    the CDCE925 could be an option as well. It is a easy to use PLL based clock synthesizer. You can input either a LVCMOS signal or a Crystal, e.g. the 10MHz, and generate up to 5x 32 MHz LVCMOS outputs.

    This device comes in a TSSOP package, so easy to solder by hand.

    Best regards,


  • Hello Andrey,

    I would like to point out to you an article a coworker and I did a few years back called, "Rework within your reach"  Soldering components such as LMK00105 is not too hard, although I would agree more challenging than a TSSOP.

      - We do have LVCMOS in LVCMOS out parts in TSSOP.  Do you require differential clock in, LVCMOS out?



  • Hello Timothy,

    Interesting. LVCMOS in LVCMOS out.

    For the time being I settled on your part CDCLVC1310. It has more outputs then I need, I hope this is not a problem