Hi All,
I am planning to use the PLL clock from the Altera cyclone IV to drive a 14bit ADC (ADS62P42). But the PLL clock has around ~140ps RMS jitter. I'll need around 3ps to take advantage of the 14bit ADC. I want to be able to change the sampling rate on the fly with the FPGA (Any where from 10~40MHz) and not have to program the jitter cleaner, is this possible?
1. Is it better to have a jitter cleaner with a crystal to drive the ADC and the FPGA, or..
2. Use a jitter cleaner to clean the clock from the FPGA to drive the ADC.
3. What is the simplest chip for this application.
-Albert