LMK04906 PLL lock problem

David Sweigart

Other Parts Discussed in Thread: LMK04906, CODELOADER

With a LMK04906 Evaluation Board (2011-12-06 v1.0), I've succeeded to up-convert a 40 MHz input clock into an 800 MHz output clock, with excellent performance characteristics. In this setup, I observed that both PLL1 and PLL2 were locked based on the LD pin. However, when using the LMK04906 chip in my PCB design, I'm no longer able to lock either PLL1 or PLL2, again based on the LD pin, despite my best efforts. I would greatly appreciate any suggestions and/or other help in understanding why the PLLs won't lock. Thank you in advance for your insight.

The register values that I'm using are given (in hexadecimal) below. Note that these values make the LMK04906 PLLs lock on the eval board but not on my custom board. Also note that three of the reserved bits conflict with the data sheet, as described in this post, but using either value doesn't appear to change the LD output behavior. I've as well tried changing various register settings, but none of the changes made the PLLs become locked (for example, I changed the PLL1_DLD_CNT from 10,000 to 1). And I'm confident that I'm programming the chip (on my custom board) successfully since I can, for instance, change the "LD_TYPE" value from "Output (push/pull)" to "Output inverted (push/pull)" and observe the LD pin toggle as expected.

REGISTER 00 : 0x00160060 (INITIAL RESET)
REGISTER 00 : 0x00140060
REGISTER 01 : 0x00140061
REGISTER 02 : 0x00140062
REGISTER 03 : 0x00140063
REGISTER 04 : 0x00140064
REGISTER 05 : 0x00140065
REGISTER 06 : 0x03340006
REGISTER 07 : 0x01310007
REGISTER 08 : 0x03030008
REGISTER 09 : 0x55555549
REGISTER 10 : 0x9642410a
REGISTER 11 : 0x0001100b
REGISTER 12 : 0x130c006c
REGISTER 13 : 0x0b13902d
REGISTER 14 : 0x1300000e
REGISTER 15 : 0x8000800f
REGISTER 16 : 0xc1550410
REGISTER 24 : 0x000000d8
REGISTER 25 : 0x02c9c419
REGISTER 26 : 0xaba8001a
REGISTER 27 : 0x1800021b
REGISTER 28 : 0x0010015c
REGISTER 29 : 0x008000dd
REGISTER 30 : 0x000000de
REGISTER 31 : 0x001f001f

Input Clock: The input clock is an OCXO with a nominal frequency of 40 MHz and a precision on the order of ppm. I'm confident that this input clock is reaching the chip's CLKin0/0* pins because I can see its LOS signal turn on when I remove the clock (and turn off when I re-apply the clock).

External VCXO: I'm operating the LMK04906 chip in the "Dual PLL, internal VCO" mode, and I'm using a 25 MHz external VCXO (Si550). I've probed the OSCout0/0* output and observed a clean 25 MHz clock, as expected. This tells me that the OSCin input to the PLL2 is indeed present.

External Loop Filters: For reference, I've provided a diagram to the bottom of this post with the external loop filters that I'm using on my custom board.

PLL1-related register settings:

PLL1_R = 8, PLL1_N = 5
PLL1_CP_POL = 1 [positive slope]
PLL1_WND_SIZE = 3 (40 ns)
PLL1_DLD_CNT = 10,000

PLL2-related register settings:

PLL2_R = 1, PLL2_N = 6, PLL2_P = 0
PLL2_CP_POL = 0 [negative slope]
PLL2_WND_SIZE = 2 [3.7 ns]
PLL2_DLD_CNT = 8,192
EN_PLL2_REF_2X = 1 [reference frequency doubled]

Other main register settings:

MODE = 0 [dual PLL, internal VCO]
CLKout0,1,2,4,5_TYPE = 3 [LVPECL (1200 mVpp)]
CLKout3_TYPE = 1 [LVDS]
CLKoutX_DIV = 3

If you'd like to have more information about my setup, please don't hesitate to ask.

over 11 years ago

0 Alan O over 11 years ago

TI__Mastermind 32575 points

What is the amplitude of the input clock at CLKIN0+/-?

What is the full part number for your VCXO? It's needed to calculate the Kv gain parameter, which affects the PLL1 loop response.

PLL2_P cannot be 0. Did you intend to type "8" instead?

Please send your CodeLoader setup file for this setup, so it is easier to load into the software and understand your device configuration.

Thanks,
Alan

0 David Sweigart over 11 years ago in reply to Alan O

Prodigy 130 points

Thank you, Alan, for looking into this PLL issue.

My 40 MHz input clock first goes through a MUX (ICS859S0212I, see attached data sheet), before arriving at the chip's CLKin0+/- pins. The amplitude of the input clock before the MUX is about 1.0 V each, yielding about 2.0 V differential; I'm attaching a PDF which shows scope traces of CLKin0+/- for this setup. Due to a mezzanine card situated above the LMK04906 chip, I'm unfortunately unable to easily probe the input to the CLKin0+/- pins directly. For reference though, I'm attaching the schematic for the LMK04906 setup on our custom board.

The full part number for our VCXO is 550BD025M000DG.

"PLL2_P = 8" is indeed what I meant to say. I typed the register value for this setting instead by mistake, which is 0x0.

I'm attaching my CodeLoader setup file for my eval board setup as well. Scope traces for this setup's (different) 40 MHz input clock are also provided in the attached PDF, which has a differential amplitude of about 2.0 V. Note that, on our custom board, we have the functionality to use an alternative input clock (labeled "ALT_CLK_IN" on our schematic), which goes through the same MUX. I have used this alternative input to send in a 3.3 V CMOS clock at 40 MHz from an SRS CG635 clock generator, but I still observe the same LMK04906 behavior where the PLLs are unlocked.

Also note that I've observed this PLL behavior for two custom boards with different LMK04906 chips.

[ICS859S0212I data sheet]

[LMK04906 setup information]

[LMK04906 schematic]

[CodeLoader setup file for eval board]

0 David Sweigart over 11 years ago in reply to David Sweigart

Prodigy 130 points

Short update:

A minor mistake on our schematic has been corrected. The 0.1 uF and 10 uF capacitors attached to the LDOBYP1 and LDOBY2 pins, respectively, needed to be swapped. This change, however, has not changed the PLL behavior.

I have also swapped our VCXO with one from a functional LMK04906 eval board, making the corresponding changes for a now single-ended output. This results, as before, in a clean 25 MHz clock at the OSCout0+/- output, and both PLLs are still reported to be unlocked by the LD output pin.

In addition, I find both PLLs to be unlocked after removing the PLL1 and PLL2 external loop filters from our custom board (with both our VCXO and the swapped-out VCXO from an eval board). With a board using our VCXO, I have even replaced these external loop filters with the component values quoted in the eval board's data sheet, but the PLLs are again reported to be unlocked.

0 Alan O over 11 years ago in reply to David Sweigart

TI__Mastermind 32575 points

Hi David,

What is the VCXO output frequency and CLKout output frequencies you're measuring? Use a high precision freq counter or spectrum analyzer to verify the frequencies with sufficient resolution (o-scopes don't give the best measurements due to sampling resolution).

For PLL1, is the input clock frequency within the absolute pull range (APR) of the VCXO? What is the CPout1 (VCXO Vc voltage) with the nominal 40 MHz input frequency? It should be near mid-rail when PLL1 is locked. If Vc voltage is railed low, it indicates the VCXO feedback divider frequency (PLL1_N div output) is higher than the reference divider frequency (PLL1_R div output). If it is railed high, it indicates the VCXO feedback divider frequency is lower than the reference divider frequency.

You can monitor the PLL1 PFD input frequency/phase on an O-scope by probing the Status_LD/_Holdover output pins aftter programming register bits LD_MUX = "PLL1_R/2" and HOLDOVER_MUX="PLL1_N/2"). The PLL1_R/2 and PLL1_N/2 means the R/N divider output is half the frequency of the PFD input frequency, in order to give 50% duty cycle outputs (instead of narrow PFD pulses which you get if you select "PLL1_R" or "PLL1_N" outputs).

Try to adjust the 40 MHz input frequency by +/- 10's~100's of PPM to see if that affects the PLL1/VCXO frequency or CPout1/Vc voltage. This could indicate if you input clock is falling inside or outside the VCXO's tuning range.

For PLL2, what is the CPout2? The same debug steps mentioned above for PLL1 can be used for PLL2. It's surprising to hear that PLL2 is not locked since the internal VCO has a wide tuning range and VCXO should be relatively stable.

I checked your CodeLoader and it seems like it should work, though i would suggest changing:
PLL2_FAST_PFD = 0
PLL2_CP_GAIN = 3200 uA
OSCout0_TYPE = LVDS (to match the LVDS termination in your schematic)

Does re-programming all the registers after all the input clock and VCXO clock are present/stable help anything?

Regards,
Alan

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LMK04906 PLL lock problem