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LMK04828 How to archiving the best jitter performance.

Kikuo Mita
Intellectual 2515 points
Other Parts Discussed in Thread: LMK04828, LMK01010

 

Hi team,

 Please advise me on archiving the best jitter performance using LMK04828.
I tried to archive the best performance generating 80MHz clock from jittery 10MHz
reference clock.
When I checked the primary PLL jitter using the Clock design tool simulation,
the 34 ps RMS jitter was archived, as long as 200 MHz VCXO was used.
If it is used with LMK01010, additional 30 ps RMS may be added.
The square root of 34 and 30 may be 45 fp.

Do you think this configuration can archive this jitter performance
or are there any things to be considered?

Mita

  • 0
    TI__Mastermind 20900 points
    Hello Kikuo,

    do you have the 200MHz VCXO available?
    if so, we need to set PLL1 to a low loop BW to filter the input noise as good as possible. 10Hz is maybe a good starting point.
    Then the cleaned 200MHz will get fed into PLL2 where we need to divide the 200MHz by 2 (max PLL2 PFD = 155MHz).
    With a loop BW of 292kHz and Phase margin of ~70 degrees, i get a rms jitter of 127fs rms (1kHz to 10MHz).

    The LMK01010 has an additive jitter of 80 fs-rms (at 200Mhz). If i choose this than I can calculate the jitter out of LMK01010 to SQRT(127^2+80^2)= 150fs rms.

    best regards,
    Julian
  • 0 in reply to Julian Hagedorn
    TI__Intellectual 2515 points

    Julian-san,

    Thank you for your advice. I can archive 127fs jitter too.

    Mita