LMK04821

Question 1 to 5 are answered in e2e.ti.com/.../1872549

6) When used in dual loop mode, the CLKin requirements in PPM would relate to the APR in PPM of the VCXO. Otherwise, the internal VCO would lock to any PPM signal. Is your question about PPM drift?

7) You can reset the LMK04821 by software by programming the RESET bit. The hard reset pin can hold the device in reset (no programming will take effect) when high. Datasheet rev AR specs minimum time of 25 ns for reset on page 22, tHIGH. No pull-down/pull-up resistor is required.. not that RESET_TYPE can be programmed for pull-down or pull-up and defaults to pull-down. Further, if you are concerned for some noise event to accidentally trigger a RESET, you can program the RESET pin for an output.

8) Depends on what is required. A basic level of SYNC is to align all the output dividers from a single device. For this a software toggle of SYNC_POL bit or toggle of physical SYNC pin, whichever is most convenient for your application, when SYNC_MODE and SYSREF_MUX are set appropriately. Please refer to datasheet section 9.3.1 and figure 13 SYNC/SYSREF clocking paths.

It is also possible to do a sync using CLKin0. I recommend this for high speed/high performance SYNC.

Since you mention just syncing one of the LMK04821 outputs, I think the software SYNC_POL toggle or SYNC pin toggle should work for you.

9) You can't change output type in sim, and actually, when you specify at the wizard page, there is a bug where it does not update the output floor as desired. My suggestion is to accept the default output types (meaning leave at any), and change the divider for other outputs to get the frequency desired. Note there is currently no difference in the sim at any given output in any output in the sim of any output, they are all simmed as equal. In reality, CLKout2 has slightly better noise floor performance.
> Clock architect is our currently supported tool and noise floor for output type sims properly.

73,
Timothy

Hello,

Power
You do not need to place separate ferrite bead for each clock group Vcc (Vcc#_CG#) if the clock output groups share the same frequency.  It is acceptable but unnecessary.  I do this for EVM because I don't know what frequencies will be on the outputs.

Inputs:
I presume that R466 will be placed closed to LMK IC.

Be aware of low impedance DC path to ground on CMOS output as is case for VCXO.  I recommend not doing this as CMOS is typically designed for driving high impedance capacitive loads.

For CVHD-037X-100 VCXO which is 3.3 V CMOS, the OSCin is specified for 2.4 Vpp max SE.  To achieve this I suggest adding a series resistor and cap to the output of X3.  So Pin 4 --> 100 ohm --> 0.1 uF --> [transmission line] --> shunt 50 ohms (R472) --> 0.1 uF (C472).

  - The cap at output of X3 prevents DC grounding the VCXO output.  The 100 ohms and 50 ohms make a voltage divider to reduce 3.3 V to an acceptable level.  To left of transmission line, place close to VCXO, to right of VCXO, place close to LMK IC.

For frequencies greater than 500 MHz I suggest a 3 dB pad for CLKin1.  R206 naturally goes close to LMK IC.

Loop Filters
Loop filter 1, R463 and cap go close to VCXO input.  Other I place closer to LMK IC output (convert current to voltage).

Loop filter 2, there is no value for R460/C441/R461/C442 unless an external VCO is being used.  As I see no external VCO being used, the 3rd and 4th pole are integrated.  I suggest you remove these components.  Please remaining filter components near LMK.

I did not not check values of loop filters as I don't have the programming info of LMK or VCXO tuning gain (although I expect I could look this up in datasheet).

Outputs:
If AC coupled, LVPECL outputs should have emitter resistors placed to ground.  I suggest 240 ohm.  Otherwise some other appropriate LVPECL termination can be used.  I don't see either.

If AC coupling LVDS/HSDS, place a 560 ohm shut resistor at output close to LMK IC.  On LMK EVM, the 560 ohm is located in a poor place far from IC.

73,
Timothy