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Clock generators, how to evaluate the synchronization of all outputs?

Stefano Infante
Expert 2310 points
Other Parts Discussed in Thread: CDCE706, CDCLVC1110, CDCLVC1102, CDCEL925, CDCE925

Hello,

I am looking for a clock generator in order to synchronize sensors in a network. My main task is that clock generator's output clocks should be as synchronous as possible, in the sense that they should not drift one with another.

My synchronization scheme has a clock generator board, which provides 20 synchronized 8.192 MHz clock outputs (these numbers are still to be confirmed). Each of these outputs needs to be carried to a different sensors board. Each board drives 4 ADCs and an RTCC, all still synchronized with the same clock.

My idea is to use a dual level scheme for the clock generator board, and a single clock generator for the sensors boards. I am now about to test CDCE706, of which I bought a few evaluation kits. it seems to be a good solution, but I have doubts about its jitter, which can reach 180 ps according to the data sheet, and it is not clear to me whether this can or cannot influence output drift.

Can you please give an advice on how I can evaluate the drift on the clock generator outputs, so that I can choose the best option?

Thanks in advance,

Stefano

  • 0
    TI__Mastermind 32575 points

    Is the below understanding of your clock generation/distribution topology correct?

    CLKGEN BOARD

    8.192 MHz XTAL --> CDCE706 --> To input of SENSOR BOARD[0:3] (4 boards)

    CDCE706 uses internal XO circuit with 8.192 MHz crystal and distributes 4 buffered copies to outputs Y[0:3].  PLL is bypassed.

    SENSOR BOARD[0:3]

    8.192 MHz CLKIN --> CDCE706 --> To inputs of 4x ADC + 1x RTCC (5 chips)

    CDCE706 simply uses the external 8.192 MHz clock input from CLKGEN board and distributes 5 buffered copies to outputs Y[0:4].  PLL is bypassed.

    If this understanding is correct, then there will be no drift between the outputs and all outputs will be synchronous.  If PLL is bypassed, the jitter will be lower than the datasheet jitter spec which assumes the PLL is used.

    From EDN article "Minimize Frequency Drift in Crystals":

    "To clarify, drift and jitter are two different sources of error for a timing device. Jitter refers to variation in the output signal or its precision. A timing source with low jitter will output a relatively consistent frequency. Drift, in contrast, describes the change in accuracy of a given frequency over environmental changes such as temperature, humidity, or pressure, or simply over long periods of time. It is measured in parts per million (ppm)."  

    Alan

  • 0 in reply to Alan O
    Expert 2310 points

    Hi Alan,

    my topology is slightly different.

    Here it is.

    CLKGEN BOARD

    8.192 MHz XTAL or oscillator --> Clock distribution device --> To input of SENSOR BOARD[0:19] (2 to 20 boards)

    The clock distribution device should have the least possible drift, so that all sensor boards are synchronous with each other, and keep their synchronization in time. CDCE706 is a choice when I need <= 6 sensor boards, but I would like to find a more general solution; I also thought about putting two levels of CDCE706 on the same board (thus reaching 36 outputs), but I don't know if it's a good idea.

    CDCE706 uses internal XO circuit with 8.192 MHz crystal and distributes 4 buffered copies to outputs Y[0:3].  PLL is bypassed.

    Your definition of sensor board is correct.

    I also have to say that all connections (CLKGEN to SENSOR boards, SENSOR board to ADCs) are on cables which do introduce some constant drift (due to the differences between lengths and cable parameters), but this drift can be, I think, in the order of nanoseconds, which is not an issue.

    I could also use something different from CDCE706 on both boards, such as clock fanout buffers or something else, as long as I don't need a PLL on CDCE706; my only need is the 32.768 kHz clock to the RTCC, which only needs a clock division. And I could use a different XTAL or oscillator at the beginning of the chain, if this can improve drift.

    Can you give an advise on how to minimize drift in this topology?

    Thanks

    Stefano

  • 0 in reply to Stefano Infante
    TI__Mastermind 32575 points

    What is the single-ended LVCMOS signaling level (1.5, 1.8, 2.5, 3.3 V?) you need for your target devices?  What supply rails do you prefer or have available for the clocks?

    For CLKGEN board, could you use the following?

    8.192 MHz XO --> CDCLVC1102 (1:2 fanout) --> 2 pcs. CDCLVC1110 (1:10 fanout) --> Up to 20 outputs (2.5V or 3.3V LVCMOS levels)

    The part-to-part skew for CDCLVC1110 is 0.5 ns MAX, so the outputs between the two buffers should be within your skew tolerance of several ns?  Also, CDCLVC1110 has footprint-compatible variants with fewer outputs so it can scale down for your design with fewer sensor boards.

    For SENSOR board, you could use CDCE925 (or CDCEL925) to buffer 4 copies of 8.192 MHz and 1 copy of 32.768 kHz (8.192 MHz / 250).

    Alan

  • 0 in reply to Alan O
    Expert 2310 points
    Hi Alan, I am not sure, but I think I will go for 3.3 V; I'll take a final decision when I will have chosen all parts.
    I find your solution very useful, because it is both complete and simple.

    Thank you very much for your help.
    Stefano