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CDCE913-Q1: CDCE913-Q1 Y1 jitter spec

Ryuuichi machida
Guru 11615 points
Part Number: CDCE913-Q1

Hi,

I would like you to confirm why jitter spec for Y1 is not described in datasheet.

According to datasheet,  jitter spec for Y2Y3 is described as shown below.

I recognized that Y1 spec is same as Y2Y3 from following E2E thread.

https://e2e.ti.com/support/clocks/int-clocks/f/50/t/457982

But, could you please tell us the reason why you do NOT describe jitter spec for Y1 ?

Best regards,

Machida

  • 0
    TI__Expert 8865 points
    Hello,

    Referring to the block diagram in the spec, Y1 was intended to be used for buffering the input clock. In this case jitter from the input clock is directly seen at Y1. But as you have seen, there are different programming options possible. If you use the Y1 similar to Y2 & Y3 (taking clock from the PLL), the same jitter spec is applicable to Y1 also.

    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Guru 11615 points

    Puneet-san,

    Thank you for your reply.

    >If you use the Y1 similar to Y2 & Y3 (taking clock from the PLL), the same jitter spec is applicable to Y1 also.

    I understand about above. But I think that TI do NOT guarantee about Y1 spec.

    So, I want you to confirm why only this spec is NOT described in datasheet. Could you please confirm it ?

    Best Regards,

    Machida

  • 0 in reply to Ryuuichi machida
    TI__Expert 8865 points
    Hi Machida-san

    Jitter on Y1 is also guaranteed and is same like for Y2 & Y3. Thanks for pointing it out.
    The reason why it was not past of the spec is only due to the reason I explained in the previous reply.
    We will update it in the datasheet and release it soon.

    Thanks & regards
    Puneet
  • 0 in reply to Puneet Sareen
    Guru 11615 points

    Hi Puneet-san,

    Thank you for your reply and sorry for my late reply.

    >The reason why it was not past of the spec is only due to the reason I explained in the previous reply.
    >We will update it in the datasheet and release it soon.

    Let me confirm one thing.

    Does above mean that you will add ATE item ? (This means that you will publish PCN or not.) ?

    I would like you to confirm whether TI did not just describe Y1 spec or not.

    Best Regards,

    Machida

  • 0 in reply to Ryuuichi machida
    TI__Expert 8865 points
    Hello Machida-san

    Y1 output jitter is also characterized in the same way like other outputs when it is configured to drive the PLL clock. But like I already mentioned, if you use Y1 as a bypass for the input clock, then jitter is dependent on the input clock. That was the main reason why it is not in the datasheet. This spec will be added to the datasheet.

    Regards
    Puneet