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CDCM6208V1F: PLL_LOCK signal implementation for reset

Tarang Jindal68
Intellectual 820 points
Part Number: CDCM6208V1F
Other Parts Discussed in Thread: CDCM6208

Hello, 

We want to connect PLL_LOCK status signal of CDCM6208 device to system reset. 

As mentioned in datasheet, if we use PLL_LOCK for System reset, then provide a RC delay. 

Please let me know that, What should be the min. RC delay filter should be used to avoid rare cycle slips ? 

It will also be useful, if you can suggest a app note for this. 

Thanks and Regards

Tarang Jindal

  • 0
    TI__Expert 8865 points
    Hi Tarang,

    Like mentioned in the datasheet, the PLL Unlock signal toggles rarely for frequency error in sub ppm range. if it toggles, the pulse width is 1000 PFD cycles. RC filter should be able to filter that.

    Regards
    Puneet