Other Parts Discussed in Thread: OMAP-L138,
Hi,
we are about to apply a CDCE906 clock synthesizer into our OMAP-L138 design. Hard- and software already works fine, in most parts.
The CDCE outputs the OMAP OSCIN clock of 24MHz, the 50MHz for the PHY and a switchable 27 / 36MHz clock for an A/D converter. It is fed from a local 24MHz XCO, so that the OMAP boots with the default setting of the CDCE906 (all 6 channels 1:1 feed through). The CDCE is controlled via I2C-Bus from the OMAP, running LINUX on the ARM core.
I have two general questions:
1st: What is the best sequence of programming the multiplier and divider registers of the CDCE906?
We have to set up three numbers into the M-Divider, N-Divider and Px-Divider registers of each PLL, and each of these registers is split up into more than one internal I2C-programmable bytes, so that we have to write a couple of bytes in sequence in order to change the output frequency. The data sheet doesn't tell much about that, and we're wondering about it, because each PLL changes its behaviour and output frequency immediately after each byte write. So frequency glitches are very likely to be expected, while setting up the PLL to a new frequency.
Our current workaround is as follows:
We set up one PLL (no. 5) to feed-through, the same as the cold start default, and switch the output multiplexer of the OMAP clock onto that PLL. Then the OMAP continues to run undisturbed and can setup other PLL registers (e g. for the ADC-frequency) step by step, while their outputs are switched off. After completing the setup we give those PLL some milliseconds to stabilize on the new frequency(s), then we switch on the output(s).
This works as long as we have no more than two PLLs to change frequency at a time - which fits for our needs currently.
Is this the recommended method of frequency setup or have you got a more detailed explenation / code example how to do it better / more easy?
2nd: We want to synchronize the master clocks (24MHz) of a couple of our systems by cabling them together. The idea is, to start each system with a local 24MHz XCO, connected to CLKIN0 of the CEDE906. The same master clock goes out to the next unit via a differential line, connected to the CLKIN1 input of the CDCE of the next system in the chain. If we then switch the clock inputs of the slave CDCEs from local XCOs to the external Clock line by an I2C command, the slave systems run on the master clock from the previous device in the chain. This works, as long the master clock is available and undisturbed. But if the master clock ceases suddenly, the OMAPs of all successors in the chain have no more clock and are unable to react.
Is it a good idea, to sense the incomming clock (CDCE input CLKIN1) by a retriggerable monflop (e.g. '122), whose low-active output is connected to the S0 control input of the CDCE? If the external clock fails within the time setting of the monoflop, e.g. 100ns, its output rises to High, re-enabling the local XCO as clock source (provided a proper setup of the CDCE registers in EEPROM). If the external clock reappears, the mono gets triggered again, selecting the external line as clock input.
Some clock chips seem to provide such a fall-back mechanism by design, but not the CDCE906, doesn't it? Or are there simpler solutions for this function available, e.g.as a separate (small, cheap, of course) chip from TI?
Thank you for any hints!
best regards Horst
