Other Parts Discussed in Thread: LMK04828, LMK04610
Hi,
I am designing an EVM for our upcoming high SNR ADC. The ADC sample rate can vary from DC to 125MHz.
It can be in either CMOS, LVDS or LVPECL format.
To achieve high SNR from ADC (>86dBFS), the sampling clock should have better than 80fs jitter.
It should be in small package with low power consumption and easy to program.
Do you think using a VCXO and clock divider chip is a workable solution here?
Do you have a clock distribution chip to suggest for this application? (may be released or in samples).
Regards,
Sourabh
