• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 20 subscribers
  • Views 332 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04616: Phase relationships of PLL2 block after Sync to align CLKout signals

Ken Hanson
Prodigy 70 points
Part Number: LMK04616

After a Sync pulse to align the CLKout signals, they will be aligned a short time after the sync pulse. Is the timing of the moment of alignment related in any way to either of the following?

1. REF signal into PLL2 block.

2. /R DIV output in PLL2 block.

Is there a detailed description available for what happens when the CLKout signals are sync'd?

  • 0
    TI__Mastermind 28550 points

    Hello Ken,

    My understanding is that the SYNC release is sampled with the prescaler output clock, so all output channels receive the RESET-deassertion on the same prescaler clock cycle.  This is illustrated somewhat in figure 33 of datasheet.

    So the SYNC it would have a relation from prscaler output clock (the clock distribution path) to PLL2 N div output, and then to PLL2 R div output because of phase lock occurring at PLL2.  Of course there could be some phase variation through the phase lock.

    73,
    Timothy