Other Parts Discussed in Thread: SN74LV123A
Hi sir
Is there a combination of logic gate and NA555 to achieve the following circuit functions?
The timing is as shown in the figure below. The three correspond to OCP_reset, U3 A pin, U2.9 signal, A channel recognizes rising edge trigger, and B channel recognizes falling edge trigger.
If you use 555, the trigger pin can only be normal high, abnormally high, abnormal to normal low, D flip-flop can be normal to normal low.
But after the state is latched, it is always low, or there is no way to return to the original state. There is no way to use a D flip-flop.
