This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2594: LMX2594 SYSREFREQ pin setup and hold

Part Number: LMX2594
Other Parts Discussed in Thread: DAC38RF89

Hello,

We are currently using the LMX2594 in SYSREF repeater mode.  The OSCin freq is 320 MHz and the SYSREF input is 80 MHz (this is matched to a DAC38RF89).  The question is with the SYSREFREQ pin setup and hold time of 2.5 ns + 2 ns minimum. Are we going to have setup and hold issues on with this regarding the OSCin clock.  I see that in this mode the SYSREF is reclocked to the Finterpolator, which in our case is something like 960 MHz. Is there a setup and hold concern in this mode and how does the SYSREF get re-clocked to the Finterpolator and then Fout?

Thanks,

Jon

  • Jonathan,

    Good to hear from you!

    The period of a 320 MHz signal is about 3 ns, yet 2.5 ns + 2 ns > 1/320MHz. So yes, you will have setup and hold issues with OSCin.

    What this means is that when you send the SysRefReq signal, you could be off by one period of the 320 MHz signal.

    Then it gets re-clocked to the phase interpolator, which is 960 MHz. Because 960 MHz phase interpolator frequency is phase locked to OSCin and is a multiple of 80 MHz, I don't think that this will be an issue with this re-clocking to the phase interpolator.

    So in summary, I think that you are likley to see a potential error of 1/320 MHz in the width of the output pulses from SysRef due to not meeting the setup and hold times of SysRefReq.

    Regards,
    Dean
  • Dean,

    Thanks for responding.  Hope you are all doing well.

    Thanks for the information.  There's no issues with metastability from the setup-hold differences?  We've run this in the lab on our setup and it works just fine.  Just wondering for when we are running over temp.

    Jon

  • Johathan,

    So it sounds like you are saying that you are not seeing any issues with 1/320 MHz variation, athough you are violating setup/hold times. The setup/hold times in the datasheet are very conservative, as they are based on design, so the numbers in the datasheet are very conservative and the true numbers are probably much tigher. My inclination is that you might not see this varaition over temperature even either, but if you do and you are violating setup/hold times, then the default TI response will be that you are violating setup/hold times.

    Regards,
    Dean