• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 21 subscribers
  • Views 441 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: Variation of VOD

Hiroshi Katsunaga
Mastermind 6480 points
Part Number: LMK04828
Other Parts Discussed in Thread: LMK04832, ADC12DJ3200, DAC38RF89

Hello,

My customer has a question about LMK04828.

[Q]

Please tell me the variation (min and max) of the VOD for the following output level.

* LVDS

* LVPECL 1600mVpp

* LVPECL 2000mVpp

It is OK as a reference value.

Best Regards,

Hiroshi Katsunaga

  • 0
    TI__Genius 16845 points

    Hi Hirsoshi,

    ΔVOD is given for LVDS in table 7.5 (page 19). It is -60mV to 60mV. Is this what you were looking for?

    Locating this information for LVPECL may require some investigation. I have assigned an engineer to look into it.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    TI__Mastermind 30410 points

    Hello Katsunaga-san,

    ΔVOD for LVPECL depends on several factors such as output frequency and emitter resistor termination. Providing minimum and maximum for the wide range of supported output frequencies and terminations is difficult.

    In the LMK04832 datasheet, we provide some examples of typical VOD for different frequencies and some different output termination styles. The output buffer design of LMK04832 is similar to the output buffer design of LMK04828.

    For what reason do you need ΔVOD for LVPECL? We may have other data that could help.

    Regards,

  • 0 in reply to Lane Boyd
    Mastermind 6480 points

    Hi Lane,

    Thank you for your fast response.

    My understanding is as follows.

    <My understanding for ΔVOD in LVDS output>

      ΔVOD is change in magnitude of VOD for complementary output states.

      For example, if DCLKoutX is 395mV then DCLKoutX* may be 395mV +/- 60mV.

      For example, if DCLKoutX is 350mV then DCLKoutX* may be 350mV +/- 60mV.

    Is my understanding correct ?

    What I want to know is not ΔVOD, but VOD min and max as described in  LMK0480x's D/S.

    I think these are not the same meaning.

    Best Regards,

    Hiroshi Katsunaga

  • 0 in reply to Derek Payne
    Mastermind 6480 points

    Hi Derek,

    Thank you for your fast response.

    I understood your comments.

    I agree it is difficult to define the LVPECL output voltage variation because it depends on several factors you mentioned.

    OK, I change the perspective of the question.

    They plan to provide the clocks from LMK04828 to ADC12DJ3200 and DAC38RF89.

    These specifications and their conditions are as follows.

    <ADC12DJ3200>

      * VID (peak-to-peak differential) for Device Clock and SYSREF : 0.4Vppd(min), 1.0Vppd(typ), 2.0Vppd(max)

      * Device Clock = 2.4GHz, AC Coupled LVPECL

      * SYSREF = 1.875MHz, AC Coupled LVPECL (Continuous)

    <DAC38RF89>

      * Vi(DPP) (peak-to-peak differential) for Device Clock and SYSREF : 800mVppd(typ), 2.0Vppd(max)

      * Device Clock = 150MHz, AC Coupled LVPECL

      * SYSREF = 1.875MHz, AC Coupled LVPECL (Continuous)

    In this case, which is better, LVPECL 1600mV or LVPECL 2000mV ?

    I want to know if the worst case of LVPECL 2000mV at 2.4GHz exceeds 2.0Vppd(max).

    Best Regards,

    Hiroshi Katsunaga

  • 0 in reply to Hiroshi Katsunaga
    Mastermind 6480 points

    Hi Lane,

    Please comment on the above questions.

    Best Regards,

    Hiroshi Katsunaga

  • 0 in reply to Hiroshi Katsunaga
    Mastermind 6480 points

    Hi Derek,

    Please comment on the above questions.

    Best Regards,

    Hiroshi Katsunaga

  • 0 in reply to Hiroshi Katsunaga
    TI__Mastermind 30410 points

    Hello Katsunaga-san,

    Apologies for the delay. Thank you for clarifying the use case.

    For the ADC12DJ3200, I strongly recommend for device clock using LVPECL 2000mV with 120Ω resistor to ground termination into the AC coupled segment. There will be enough attenuation that the typical VID for device clock should never exceed 2.0Vppd. The SYSREF can be LVPECL 1600mV since it is much lower frequency.

    For the DAC38RF89, the device clock and SYSREF are both low enough frequency that LVPECL 1600mV should meet the required spec without trouble.

    Worst case LVPECL 2000mV at 2.4GHz will not exceed 2.0Vppd(max).

    Regards,

  • 0 in reply to Derek Payne
    Mastermind 6480 points

    Hi Derek,

    Thank you for your response and your clear comments.

    OK, I understood your comments.

    I will share your comment with my customer.

    Thank you for your cooperation.

    Best Regards,

    Hiroshi Katsunaga